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d a t a sh eet objective speci?cation 2004 mar 22 integrated circuits UJA1061 low speed can/lin system basis chip
2004 mar 22 2 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 contents 1 features 1.1 general 1.2 system features 1.3 fail-safe features 1.4 can physical layer 1.5 lin physical layer 2 general description 3 ordering information 4 block diagram 5 pinning 6 functional description 6.1 introduction 6.2 fail-safe system controller 6.2.1 fail-safe mode 6.2.2 start-up mode 6.2.3 restart mode 6.2.4 normal mode 6.2.5 standby mode 6.2.6 sleep mode 6.2.7 flash mode 6.3 on-chip oscillator 6.4 watchdog 6.4.1 watchdog start-up behaviour 6.4.2 watchdog window behaviour 6.4.3 watchdog time-out behaviour 6.4.4 watchdog off behaviour 6.5 system reset 6.5.1 system reset pin rstn 6.5.2 enable output pin en 6.6 power supplies 6.6.1 supported battery systems 6.6.2 static and dynamic battery monitoring 6.6.3 voltage regulators v1 and v2 6.6.4 switched battery output (v3) 6.7 can transceiver 6.7.1 mode control 6.7.2 termination control 6.7.3 bus, rxd and txd failure detection 6.8 lin transceiver 6.8.1 mode control 6.8.2 bus and txdl failure detection 6.9 inhibit output (pin inh) 6.10 wake-up input (pin wake) 6.11 interrupt output 6.12 temperature protection 6.13 spi interface 6.14 spi register mapping 6.14.1 register overview 6.14.2 mode register 6.14.3 system status register 6.14.4 system diagnosis register 6.14.5 interrupt enable register 6.14.6 interrupt enable feedback register 6.14.7 interrupt register 6.14.8 system configuration register 6.14.9 system configuration feedback register 6.14.10 physical layer control register 6.14.11 physical layer control feedback register 6.14.12 special mode register 6.14.13 general purpose registers 6.14.14 general purpose feedback registers 6.15 register configurations at reset 6.16 test modes 6.16.1 software development mode 6.16.2 forced normal mode 7 limiting values 8 dc characteristics 9 ac characteristics 10 package outline 11 soldering 11.1 introduction to soldering surface mount packages 11.2 reflow soldering 11.3 wave soldering 11.4 manual soldering 11.5 suitability of surface mount ic packages for wave and reflow soldering methods 12 data sheet status 13 definitions 14 disclaimers
2004 mar 22 3 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 1 features 1.1 general excellent emc performance 8 kv esd protection (human body model) for the outside module pins can/lin-bus pins are short-circuit proof to the battery (up to 60 v) and to ground battery and can/lin-bus pins are protected against transients that occur in an automotive environment (iso7637) software development mode partly disabling of fail-safe and watchdog functionality to ease software development unique spi readable device type identification small footprint htssop32 package (body 6 11 mm) with low thermal resistance. 1.2 system features 12 v, 24 v and 42 v system support with low sleep current (typical 50 m a) support of 2.5, 3.0, 3.3 and 5.0 v microcontrollers with automatic adaption of interface levels to microcontrollers flexible, independent external regulator extension via 14 v battery related pin inh (enables fail-safe scalable supply system) smart operating and power management modes in-field flash programming mode cyclic wake-up capability in standby and sleep mode remote wake-up capability via can and lin buses local wake port with cyclic supply feature 42 v battery related local wake-up input 42 v battery related high-side switch output to drive external loads such as relays and wake-up switches interrupt output with 12 maskable interrupt sources: C interrupt service monitor C one interrupt per watchdog period to prevent microcontroller overloading; ensures predictable software behaviour extensive set of spi-readable system diagnostics: C detection and detailed error reporting on can and lin bus failures (e.g. shorts to gnd/bat, open bus wires, etc.) C txd dominant and rxd recessive clamping as well as rxd to txd short detection to prevent bus deadlocks C local ecu ground-shift detection with two selectable thresholds C over-temperature warning C battery monitoring to detect battery interrupt or a chattering battery contact to store data before microcontroller power down (e.g. to store seat position) C signalling of potential ram-retention errors due to low microcontroller v cc . 1.3 fail-safe features programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision fail-safe coded 16-bit spi interface to microcontroller, including chip-select pin for multiple spi devices on the same bus integrated fail-safe and system features: C rigorous error handling based on diagnostics C 12 dedicated reset sources supporting different, history dependent, software start-up and diagnosis C global enable pin for control of safety critical hardware C limp home output signal for activating application hardware in case system enters fail-safe mode (e.g. switch on parking lights) C single spi message; no assembly of multiple spi frames C programmable active-low system reset with detection of both clamped and open reset line to prevent system deadlocks C fail-safe coded activation of software development mode and flash mode C 24-bit access-protected ram can be used, for instance, for logging of cyclic problems.
2004 mar 22 4 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 1.4 can physical layer iso11898-3 compliant fault-tolerant can transceiver downwards compatible with tja1054/tja1054a enhanced error signalling and reporting separated low-drop-out voltage regulator for can bus: C microcontroller supply independent, autonomous physical layer bus failure management C significantly improves emc performance partial networking capability: C completely passive behaviour to the bus when unpowered C selective sleep option with global wake-up allowing selected can bus communication without waking-up sleeping nodes. 1.5 lin physical layer lin2.0 compatible lin transceiver enhanced error signalling and reporting. 2 general description the UJA1061 is a system basis chip (sbc), replacing basic discrete components that are commonly used in electronic control units (ecus) for automotive body multiplexing. the UJA1061 supports any body application which controls various power peripherals by using the fault-tolerant can as the main physical layer and the lin physical layer as local sub-bus. the UJA1061 contains the following integrated devices: low speed, fault-tolerant can transceiver, inter-operable and downwards compatible with can transceivers tja1054 and tja1054a, and compatible with iso11898-3 standard lin transceiver compatible with lin specification, revision 2.0 watchdog separate voltage regulators for both host controller and can transceiver serial peripheral interface (full duplex) local wake-up input port inhibit output port. in addition to the cost advantages compared with conventional multi-chip solutions, the UJA1061 offers an intelligent combination of system-specific functions such as: advanced low power concept safe and controlled system start-up behaviour advanced fail-safe system behaviour that prevents any deadlock detailed status reporting on system and sub-system (for example, can) levels. the UJA1061 is intended to be used in combination with a microcontroller and a can controller. the microcontroller is the first to come and the last to go in an ecu designed with the UJA1061. in failure situations, the UJA1061 maintains the microcontroller function as long as possible in order to provide full monitoring and software driven fall-back operation. the UJA1061 can be operated in: single 42 v power supply architecture when combined with an external step-down converter single 14 v power supply architecture dual 14 v and 42 v power supply architecture. 3 ordering information note 1. add suffix to indicate version: * = 5v0 for 5 v version * = 3v3 for 3.3 v version * = 3v0 for 3 v version * = 2v5 for 2.5 v version. type number (1) package name description version UJA1061tw/* htssop32 plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad sot549-1
2004 mar 22 5 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 4 block diagram mce622 fail-safe system controller lin transceiver bat42 n.c. gnd rxdl txdl lin rtlin scs sdo sdi sck intn inh/limp wake bat14 18 sense 31 bat42 32 bat14 27 sysinh 29 v3 30 17 7 11 9 10 12 1, 2, 15, 28 26 25 3 5 23 bat42 v2 fault tolerant can transceiver v2 regulator v1 regulator UJA1061 battery monitor wake inh ram status chip temperature reset/enable osc rxdc txdc canl canh rtl rth 14 13 22 21 19 24 test (gnd) v2 16 v2 20 rstn 6 en 8 v1 4 ground shift detector watchdog serial peripheral interface termination fig.1 block diagram.
2004 mar 22 6 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 5 pinning symbol pin description n.c. 1 not connected n.c. 2 not connected txdl 3 transmit data input to activate the lin output drive; low = lin-bus dominant; high = lin-bus recessive v1 4 regulated supply voltage output for microcontroller; voltage is 5 v, 3.3 v, 3 v or 2.5 v according to version rxdl 5 receive data output for reading data from the lin-bus; low when lin-bus is dominant; high when lin-bus is recessive rstn 6 active low push-pull output used to reset the microcontroller; the UJA1061 also monitors the voltage on pin rstn for any clamping situation (fail-safe) intn 7 active low open-drain output used to interrupt the microcontroller; pin intn is to be wire-anded with other interrupt outputs within the ecu en 8 push-pull enable output related to voltage regulator v1; active high if the watchdog is triggered successfully and a control bit is set; immediately pulled low with any reset event (e.g. a watchdog over?ow); full set/clear application access via spi while watchdog is served properly sdi 9 spi data input sdo 10 spi data output sck 11 spi clock input scs 12 active low select input used to enable an spi access txdc 13 transmit data input that activates the can output driver; low = can-bus dominant; high = can-bus recessive rxdc 14 receive data output for reading data from the can-bus; low when can-bus is dominant; high when can-bus is recessive; output is continuously low upon a wake-up event received via the can-bus n.c. 15 not connected test 16 test pin; connect to ground in application inh/limp 17 14 v battery related inhibit output for system extension, or limp home output, activated in fail-safe mode (default ?oating) wake 18 42 v battery related local wake-up input rtl 19 can termination resistor connection; in case of a canl bus wire error this line is terminated with a selectable impedance v2 20 regulated 5 v supply output reserved for can transceiver; an external buffer capacitor connects to this pin canh 21 can-bus line; high in dominant state and low in recessive state canl 22 can-bus line; low in dominant state and high in recessive state gnd 23 ground rth 24 can termination resistor connection; in case of a canh bus wire error this line is terminated with a selectable impedance lin 25 lin-bus line; low when lin-bus is dominant, high when lin-bus is recessive rtlin 26 lin-bus termination resistor connection bat14 27 14 v battery supply input n.c. 28 not connected
2004 mar 22 7 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 sysinh 29 42 v inhibit (controlling an external 42 v to 14 v dc-to-dc converter, for example) v3 30 unregulated 42 v supply output, continuous and cyclic modes for supply of wake-up switches, cyclic mode synchronized with local wake input ports sense 31 fast battery interrupt/chatter detector input bat42 32 42 v battery supply input; protected up to 60 v symbol pin description UJA1061 n.c. bat42 n.c. sense txdl v3 v1 sysinh rxdl n.c. rstn bat14 intn rtlin en lin sdi rth sdo gnd sck canl scs canh txdc v2 rxdc rtl n.c. wake test inh/limp mce623 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 20 19 22 21 24 23 26 25 32 31 30 29 28 27 fig.2 pin configuration.
2004 mar 22 8 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6 functional description 6.1 introduction the UJA1061 combines all peripheral functions around a microcontroller within typical automotive body multiplexing applications into one dedicated chip. the functions are: power supply for host microcontroller power supply for can physical layer switched bat42 output system reset watchdog with window and time-out modes on-chip oscillator fault-tolerant can and lin physical layers for serial communication suitable for 12 and 42 v applications spi control interface local wake-up input inhibit output, or limp home output system inhibit output port compatibility with 42 v power supply systems fail-safe behaviour. 6.2 fail-safe system controller the fail-safe system controller is the heart of the UJA1061 and is controlled mainly by the watchdog, which is clocked directly via a dedicated, on-chip oscillator. it handles the register configuration and controls all internal functions of the UJA1061. the device status information is collected and reflected to the microcontroller. also the reset and interrupt signals are provided by the system controller. the system controller is a state machine. the different levels of operation provided are represented in fig.3. 6.2.1 f ail - safe mode during severe fault situations the UJA1061 always enters its fail-safe mode (see also fig.3). this mode has the lowest possible system power consumption. these fault situations are: on-chip oscillator failure (frequency too low). fail-safe mode is entered from any other mode immediately after this failure is detected pin rstn is clamped high for more than 128 ms while the UJA1061 tries to drive pin rstn low. the fail-safe mode will be entered immediately out of any other mode in which the UJA1061 tries to drive pin rstn low (start-up, standby or sleep mode) after detecting this failure pin rstn is clamped low for more than 256 ms after the UJA1061 has released the pin rstn internally in start-up or in restart mode a falling edge on pin rstn during the initialization phase in restart mode no successful initialization of normal mode within 256 ms after pin rstn has become high in restart mode whereby that the software-controlled software development mode is not active wrong mode register code within restart mode wrong spi count within restart mode low v1 regulator output for more than 256 ms due to a too-high load or a short-circuit of v1 to ground in start-up mode low v1 regulator output directly after an already-released pin rstn in restart mode. the following events cause the system to exit the fail-safe mode if the on-chip oscillator is running correctly: activity on the can-bus activity on the lin-bus activity on pin wake. the UJA1061 restarts out of fail-safe mode and enters start-up mode to give the application a new opportunity to start. regulator v1 starts again and the reset pulse will be set to the long period (see section 6.5.1). 6.2.2 s ta rt - up mode start-up mode is entered after a number of events that result in a system reset (see fig.3) and is the first opportunity for the system to start-up. these events are: the first battery and ground connection of the module whereby the power supply v1 for the host microcontroller becomes active for the first time. the UJA1061 provides a power-on reset for the system. as this is the first connection of the battery, the UJA1061 has no indication of the reset length required by the host microcontroller, therefore the long reset sequence is chosen as default
2004 mar 22 9 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 an external reset event is applied to the reset input of the UJA1061. here, if pin rstn was already high before the event (as in normal, standby or flash mode), any other operating mode of the UJA1061 is left immediately and the external reset pulse is lengthened by the UJA1061 to the user-defined reset period. an external reset event does not allow the UJA1061 to be forced back to start-up mode out of restart or fail-safe mode to deal with a chattering and/or a clamped reset line. in such a case, the system has to end within fail-safe mode with the lowest possible power consumption. an undervoltage is detected at the v1 supply. in this case any other operating mode of the UJA1061 in which v1 was active (normal, start-up or flash mode) is left immediately and the external reset pulse is lengthened by the UJA1061 to the user-defined reset period. further undervoltage conditions do not allow the UJA1061 to be forced out of restart or fail-safe mode in order to deal with continuous undervoltages on v1. the system has left the fail-safe condition due to a wake-up event with a running oscillator. here again the long reset period is applied in order to guarantee a proper system start. when the reset period is finished (pin rstn is released and goes high) the watchdog waits for initialization. if the watchdog initialization is correct, the selected operating mode is entered. the only correct watchdog initialization out of start-up is a successful spi access of the mode register, whereby the init normal mode or init flash mode is selected. as start-up mode is the home page of the UJA1061, below a mode-oriented overview of the events, which result in a mode transition towards start-up mode. being in sleep mode, start-up mode will be entered using the user-defined reset pulse if: activity on the can-bus or lin-bus is detected a falling edge on the local input port is detected a watchdog time-out occurs (used for cyclic wake-up of the module) a failure at the v3 power supply pin occurs (only if v3 is active). being in fail-safe mode, start-up mode will be entered using the long reset pulse if: activity on the can-bus or the lin-bus and the oscillator functions correctly again a falling edge on the local input port is detected and the oscillator functions correctly again. being in normal, standby or flash mode, start-up mode will be entered if: a falling edge on pin rstn is detected. if pin rstn is held low externally for a long period, fail-safe mode will be entered directly since a serious ecu problem exists an unwanted undervoltage condition at v1. in the case where v1 is active and then falls below the undervoltage detection threshold the UJA1061 immediately enters start-up mode forcing pin rstn low. if v1 keeps within the undervoltage condition for a long time, this again is an indication of a malfunctioning application and the UJA1061 enters fail-safe mode without first entering restart mode. a reset as a result of this condition can occur only when v1 was already active with a high level on pin rstn start-up mode also will be entered out of standby mode on the following events (restarting a continuously powered microcontroller with a user-defined reset pulse): a wrong mode register code access occurs the microcontroller supply current increases as a result of an externally activated microcontroller in the watchdog off mode if the reset option is selected a watchdog time-out did occur if the reset option is selected activity on the can-bus or lin-bus is detected if the reset option is selected, even if the microcontroller did request a change to sleep mode during a pending wake-up a falling edge on the local input port is detected if the reset option is selected, even if the microcontroller did request a change to sleep mode during a pending wake-up after an ignored interrupt. depending on the application software, certain events can force an interrupt or a reset event. in the case of interrupts, these interrupt events have to be served by the application software within 256 ms. if the software does not react within this time, the UJA1061 will force a transition into start-up mode with a defined reset behaviour.
2004 mar 22 10 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 being in normal mode, start-up mode will be entered if: a wrong mode register code access occurs on too-late or too-early watchdog triggering after an ignored interrupt (same as an ignored interrupt in standby mode) flash mode entry sequence is written to the mode register during a pending wake-up when the microcontroller did request a mode change to sleep mode. being in flash mode, start-up mode will be entered if: a wrong mode register code access occurs on a watchdog trigger overflow (too late) after an ignored interrupt (same as an ignored interrupt in standby mode). when entering start-up mode, the reset source information is provided by the UJA1061 in order to support different software initialization cycles that depend on the reset event. 6.2.3 r estart mode the intention of the restart mode is to give the application a second opportunity to start-up, if the first start-up has failed due to a certain failure. restart mode will be entered out of the start-up as shown in the state diagram (see fig.3). the events are as follows: a watchdog initialization failure occurs (wrong mode register code or start-up time-out an spi failure (spi count other than 16) occurs a falling edge on pin rstn occurs during the initialization phase in start-up mode a falling edge on pin rstn occurs during start-up. entering restart mode will always lengthen the reset pulse to the long period in order to guarantee a proper reset length independent from history. if one of these failures still occurs after entering this mode; pin rstn stays low or if the UJA1061 detects an undervoltage on v1 after an already released pin rstn, fail safe mode will be entered. if the failure has been removed during restart mode and the watchdog initialization has been successful, the selected operating mode will be entered. the only correct watchdog initialization out of restart mode is the spi access of the mode register, whereby the init normal mode has been selected. 6.2.4 n ormal mode the normal mode is entered after the following events (see fig.3): watchdog initialization has been executed successfully after an init normal mode access of the mode register out of start-up or restart mode out of standby mode via an spi command. in this mode the UJA1061 allows access to all system resources such as can, lin, inh and en and therefore requires accurate watchdog triggering using the window mode with programmable windows. upon any false watchdog trigger, a system reset is performed. interrupts to the host microcontroller initiated by the UJA1061 are also observed. a system reset is performed if the host microcontroller does not react within 256 ms. entering normal mode does not activate the can physical layer automatically. a certain bit (can mode) is used to activate the can medium if desired, enabling local cyclic wake-up scenarios to be implemented without affecting the can physical layer. 6.2.5 s tandby mode standby mode sets the system into a state with reduced current consumption. entering standby mode will automatically clear the can mode bit, thus allowing the can physical layer to enter the low-power mode autonomously. however, the watchdog still monitors the microcontroller (time-out mode) since it is powered via pin v1. in case the host microcontroller can provide a low-power mode with reduced current consumption in its standby or stop mode, the watchdog can be switched-off entirely within standby mode of the UJA1061. the UJA1061 monitors the microcontroller supply current to make sure that there is no unobserved phase with disabled watchdog and running microcontroller. the watchdog will keep active until the supply current drops below a certain limit. below this current limit the watchdog is disabled. if the current increases again, e.g. caused by a microcontroller wake-up from application-specific hardware, the watchdog starts operation again with the previously-used time-out period. a system reset can be performed if programmed accordingly, in this case start-up mode is entered.
2004 mar 22 11 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 if standby mode is entered out of normal mode with selected watchdog-off option, the watchdog uses the maximum time-out defined for standby mode until the supply current drops below the current detection threshold. now the watchdog is off. if the current increases again the watchdog will become active immediately using the maximum watchdog time-out period again. generally, the microcontroller can be activated out of standby mode via a system reset or via an interrupt without reset. this allows different start-up behaviours out of standby mode to be implemented, depending on application needs: if the watchdog is still running during standby mode, the watchdog can be used for cyclic wake-up behaviour of the system. a dedicated watchdog time-out interrupt enable (wte) bit allows a decision whether the microcontroller should receive an interrupt or a hardware reset upon overflow. the interrupt option will be cleared in hardware automatically with each watchdog overflow to make sure that a failing main routine is detected while the interrupt service still operates. therefore the application software must set the interrupt behaviour again before the next standby cycle is entered. any wake-up via the can or the lin bus as well as a local wake-up event will force a system reset event or an interrupt to the microcontroller. so it is possible to leave standby mode without any system reset if desired. upon an interrupt event the application software has to read the interrupt register within 256 ms. if this is not executed, the fail-safe system reset is forced and start-up mode is entered. if the application has read out the interrupt register in time, it can decide to switch into normal mode via spi access or to stay in standby mode. the following operations are possible within standby mode: cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the microcontroller is triggered periodically and checked for the correct response) cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically; the UJA1061 provides information about the reset source in order to allow different start sequences after reset) wake-up by bus activity on can or lin via an interrupt signal to the microcontroller wake-up by bus activity on can or lin via a reset signal wake-up by increasing microcontroller supply current without a reset signal (where a stable supply is needed for the microcontroller ram contents to remain valid and wake-up comes from an external application not connected to the UJA1061) wake-up by increasing microcontroller supply current with reset signal wake-up due to an edge at pin wake forcing an interrupt to the microcontroller wake-up due to an edge at pin wake forcing a reset signal. 6.2.6 s leep mode within sleep mode the microcontroller power supply (v1) and the inh controlled external supplies are switched off entirely thus resulting in minimum system power consumption. in this mode, the watchdog runs in time-out mode or is completely off. entering sleep mode results in an immediate low level on pin rstn, thus stopping any operation of the microcontroller. in parallel, the inh output is floating and pin v1 is disabled. only sysinh could remain active to support the v2 voltage supply; this depends on can programming. it is also possible for v3 to be on, off or in cyclic mode in order to supply external wake-up switches. if the watchdog is not disabled in software, the watchdog keeps running and forces a system reset upon overflow of the programmed period time. the UJA1061 enters start-up mode and pin v1 becomes active again. this behaviour could be used for a cyclic wake-up out of sleep mode. entering sleep mode can be done only from normal mode or from standby mode with a mode change via the spi. depending on the application, the following operations are selectable within sleep mode: cyclic wake-up by the watchdog (only in time-out mode); a reset is performed periodically, the UJA1061 provides information about the reset source in order to allow different start sequences after reset wake-up by bus activity on can or lin wake-up due to a falling edge at pin wake an overload on v3, only if v3 is in a cyclic or in continuously-on mode.
2004 mar 22 12 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 mce624 normal v1: on sysinh: high v3: on/off/cyclic inh: high/floating can: active/auto lin: active watchdog: window en: high/low flash v1: on sysinh: high v3: on/off/cyclic inh: high/floating can: active/auto lin: active watchdog: time-out en: high/low standby v1: on sysinh: high v3: on/off/cyclic inh: high/floating can: auto lin: off-line watchdog: time-out/off en: high/low start-up v1: on sysinh: high v3: on/off/cyclic inh: high/floating can: auto lin: off-line watchdog: start-up en: low restart v1: on sysinh: high v3: on/off/cyclic inh: floating can: auto lin: off-line watchdog: start-up en: low fail-safe v1: off sysinh: high/floating v3: unchanged inh: floating can: auto lin: off-line watchdog: off rstn: low en: low sleep v1: off sysinh: high/floating v3: on/off/cyclic inh: floating can: auto lin: off-line watchdog: time-out/off en: low out of start-up/restart/sleep wrong mode register code or interrupt ignored > 256 ms or (watchdog off and i v > i v1(min) with reset option) or (watchdog time-out with reset option) or (wake-up with reset option) and mode change via spi to sleep with pending wake-up user defined reset pulse at pin rstn rstn externally forced falling edge v3: unchanged inh: floating flash entry = disabled out of normal/standby/ flash mode only out of normal/standby/ flash mode only v1 is active and v1 undervoltage rstn: low inh: floating bat and gnd connected first time long reset pulse at pin rstn v3: off inh: floating rstn falling edge or (t > 256 ms and sdm = logic 0) or (wrong mode register code and sdm = logic 0) or spi clock count < or > 16 or rstn = low > 256 ms or (rstn = high and v1 undervoltage) (rstn falling edge and sdm = logic 0) or (t > 256 ms and sdm = logic 0) or wrong mode register code or spi clock count < or > 16 flash entry disabled long reset pulse at pin rstn event action watchdog trigger mode change via spi rstn forced low watchdog trigger mode change via spi mode change via spi mode change via spi rstn forced low watchdog trigger init normal mode via spi successful flash entry = disabled init flash mode via spi and flash entry enabled flash entry = disabled wrong mode register code or [sdm = logic 0 and (watchdog overflow or interrupt ignored > 256 ms)] user defined reset pulse at pin rstn init normal mode via spi successful oscillator fail (rstn = high and rstn driven low and sdm = logic 0) > 128 ms flash entry enabled via mode sequence 111/001/111 or wrong mode register code or [sdm = logic 0 and (watchdog trigger too early or watchdog overflow or interrupt ignored > 256 ms)] or mode change via spi to sleep with pending wake-up user defined reset pulse at pin rstn watchdog time-out or wake-up or v3 overload user defined reset pulse at pin rstn wake-up and recovered osc fail long reset pulse at pin rstn reset code = wake-up out of fall-safe (v1 is active and v1 undervoltage > 256 ms) or (v1 ok and rstn = low > 256 ms) flash entry = disabled fig.3 main state diagram UJA1061. sdm = logic 0 represents the normal watchdog behaviour.
2004 mar 22 13 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.2.7 f lash mode flash mode can be entered only from start-up mode if a certain fail-safe mode control sequence has been applied to the UJA1061 within normal mode. this control sequence comprises three consecutive write accesses to the mode register within the legal windows of the watchdog using the mode codes 111, 001 and 111 respectively. as a result of this sequence, the UJA1061 enters start-up mode providing a system reset and the related reset source information. within start-up mode, the application software has the 256 ms start-up time available to enter flash mode, using the init flash code 011 within the mode register thus feeding back a successfully received hardware reset (handshake between UJA1061 and microcontroller). this transition towards flash mode is possible only once after the above fail-safe entry sequence. the application can also decide not to enter flash mode but switch over to normal mode again using the init normal mode code 101 for handshaking. this again clears the prepared fail-safe flash mode entry. so if the flash mode should be entered again, the fail-safe sequence has to be applied again. the watchdog behaviour within flash mode is similar to its time-out behaviour within standby mode, however the mode code 111 has to be used for serving the watchdog. if this code is not used or the watchdog overflows, the UJA1061 immediately forces a reset and enters start-up mode again. this allows leaving flash mode very quickly with a defined reset and without waiting for a watchdog overflow. 6.3 on-chip oscillator the on-chip oscillator provides the clock signal for all digital functions and is the time reference for the on-chip watchdog and the internal timers. if the on-chip oscillator frequency is too low or the oscillator is not running there is an immediate transition to fail-safe mode. the UJA1061 will stay within fail-safe mode until the oscillator has recovered to its normal frequency and the system receives a wake-up event. there is no possibility to have a system running without watchdog supervision or with erroneous watchdog supervision. 6.4 watchdog the watchdog fulfils the following basic tasks: verifies proper microcontroller start-up continuously monitors the microcontroller and performs a reset whenever the microcontroller fails to trigger the watchdog in time (according to the selected mode) applies a cyclic wake-up to the sleeping microcontroller. the watchdog is clocked directly by an independent on-chip oscillator. in order to guarantee fail-safe control of the watchdog via the spi, all watchdog accesses are coded with redundant bits. therefore only certain codes are allowed for a proper watchdog service. the following corrupted watchdog accesses are detected and result in an immediate system reset: illegal watchdog period coding; only ten different codes are valid illegal operating mode coding; only six different codes are valid a mode other than init normal mode or init flash mode is selected during the watchdog initialization phase. furthermore, any spi access is monitored with respect to the number of clock (sck) cycles. if enabled, an interrupt is forced whenever the clock count differs from 16 clock periods. within start-up and restart mode a system reset instead of an interrupt is forced immediately in the event of an incorrect number of clock counts. any microcontroller-driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information within the same register. this allows an easy software flow control with defined watchdog behaviour when switching between different software modules. the watchdog, as an independent observation medium of the microcontroller, provides the following timing functions: start-up mode; needed to give the software an opportunity to initialize the system window mode; detects too early and too late accesses within normal mode time-out mode; detects a too late access; can also be used to restart or interrupt the microcontroller from time to time off mode; fail-safe shut-down during operation thus preventing any blind-spots in system supervision.
2004 mar 22 14 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.4.1 w atchdog start - up behaviour within start-up and restart mode of the UJA1061, the watchdog offers its start-up behaviour. in this mode the watchdog monitors pin rstn (input) to check whether it becomes released or is clamped externally. any time pin rstn stays low longer than the reset monitoring period, this is interpreted as a clamping situation and the corresponding mode change of the UJA1061 is performed. once the reset pin has been released within the reset monitoring period the start-up period begins (see fig.4). if the microcontroller does not initialize the watchdog within this time frame, the watchdog restarts the system via the reset output and enters restart mode. the whole procedure with the reset monitoring period and the start-up period repeats. if pin rstn is low for too long, or the microcontroller did not initialize the watchdog within the time, fail-safe mode will be entered. if pin rstn has been released and the initialization phase is entered, a falling edge on pin rstn results immediately in a transition from start-up to restart mode, or from restart to fail-safe mode (fail-safe behaviour in case of chattering reset events). if pin rstn is held low internally by the UJA1061, due to a low voltage situation at pin v1 caused, for example, by a short-circuit, the watchdog again monitors this time. after the reset monitoring period, fail-safe mode is entered and pin v1 is disabled. so, independently from the cause of a reset event, the watchdog starts the reset monitoring period whenever pin rstn is pulled low. during the start-up period, the UJA1061 accepts write access to the general purpose registers, the special mode register (once after the first supply connection only) and the mode register only. mce625 start-up period rst monitoring period start-up period rst monitoring period (1) (2) (3) (4) (5) pin rstn input watchdog period < 256 ms start-up restart < 256 ms < 256 ms < 256 ms fig.4 reset monitoring and start-up period. (1) UJA1061 releases pin rstn after 1 ms or 20 ms. (2) external hardware releases pin rstn. (3) watchdog initialization fails. (4) 20 ms reset period. (5) external hardware releases pin rstn.
2004 mar 22 15 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.4.2 w atchdog window behaviour whenever the UJA1061 has entered normal mode as a result of a successful watchdog initialization, the window mode of the watchdog has been activated. this makes sure that the microcontroller operates within the desired speed. too fast as well as too slow operation will be detected. see fig.5 for watchdog triggering using the window mode. the UJA1061 provides ten different period timings in this mode (with an accuracy of 10 %). the watchdog window has been defined to be between 50 and 100 % of the nominal programmed watchdog period. the period can be changed on the fly with any valid spi mode register access. whenever the watchdog is triggered within the window time, the timer is reset in order to start a new period. any too early or too late watchdog access or wrong mode register code access results in an immediate system reset, entering start-up mode. in the background, any enabled interrupt event will be monitored by the watchdog. if the microcontroller does not react upon receipt of an interrupt within the interrupt response time (265 ms), a system reset will be performed. handbook, full pagewidth mce626 trigger window trigger window too early trigger restarts period 50 % trigger via spi trigger via spi last trigger point earliest possible trigger point latest possible trigger point earliest possible trigger point latest possible trigger point too early trigger restarts period (with different duration if desired) period 100 % 50 % 100 % new period fig.5 watchdog triggering using window mode.
2004 mar 22 16 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.4.3 w atchdog time - out behaviour whenever the UJA1061 operates in standby mode, in sleep mode or in flash mode, the watchdog is operated in time-out mode. the watchdog has to be triggered within the actual programmed period time (see fig.6). the time-out mode can be used to provide cyclic wake-up events to the host microcontroller during low-power modes. in standby and in flash mode the nominal periods can be changed with any spi access to the mode register. since in sleep mode regulator v1 is off and the microcontroller is not powered, no further change of the time-out period is possible. any wrong mode register code access results in an immediate system reset, entering start-up mode. 6.4.4 w atchdog off behaviour within standby and sleep mode, the watchdog off behaviour can be selected in order to disable the watchdog entirely. if the watchdog is triggered with the watchdog off code while the UJA1061 is in standby mode, or while the UJA1061 enters standby mode, the v1 current monitoring function stays disabled for a period of time equal to the previous or the default (4096 ms) watchdog period. the default period is selected if the standby mode is entered directly with watchdog off mode. after that period the current monitoring is enabled. then the behaviour of the UJA1061 upon a too-high v1 current depends on the setting of the v1cmc bit within the system configuration register. if bit v1cmc is set (reset option) a too-high v1 current causes immediately a reset. if bit v1cmc is not set (watchdog restart option), the watchdog starts a new period without the possibility to disable it except by triggering it again with the watchdog off code. if the watchdog off code is chosen the watchdog time-out interrupt has no function. if the watchdog off behaviour has been entered successfully and later on pin v1 current increases again, the watchdog starts operating with the previously programmed time-out period. in case standby mode is entered directly out of normal mode with watchdog off behaviour coding, the watchdog keeps running with its maximum time period until pin v1 current falls below the threshold. if the current increases again, the maximum period is used again. if sleep mode is entered together with the watchdog off behaviour, the UJA1061 immediately forces pin rstn to low level. in parallel, pin v1 is disabled and the watchdog is stopped. handbook, full pagewidth mce627 trigger via spi earliest possible trigger point latest possible trigger point trigger restarts period (with different duration if desired) new period trigger range trigger range time-out time-out period fig.6 watchdog triggering using time-out mode.
2004 mar 22 17 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.5 system reset the reset function of the UJA1061 offers two signals to deal with reset events: rstn; the global ecu system reset en; a fail-safe global enable signal. 6.5.1 s ystem reset pin rstn the system reset pin rstn is a push-pull bidirectional input/output. pin rstn is active low with selectable pulse length upon the following events (see fig.3): power on (first battery connection) or bat42 below power-on reset threshold voltage v1 power on (wake-up out of sleep mode), indicated as cyclic wake-up out of sleep low v1 supply v1 current above threshold during standby mode while watchdog off behaviour is selected v3 is down due to short-circuit condition during sleep mode rstn externally forced low, falling edge event successful preparation for flash mode completed; flash mode can be entered now wake-up out of standby mode via can, lin or wake while reset behaviour is selected; or wake-up out of sleep mode via can, lin or wake wake-up event out of fail-safe mode watchdog trigger failures (too early, too late, overflow, time-out/not initialized in time, wrong code) illegal mode code via spi applied interrupt not served within 256 ms. all these events resulting in a reset have dedicated flags in order to distinguish between the different events. the only exception is the combination of the following two different reset sources: the power on (first battery connection), or pin bat42 below power-on reset threshold voltage and pin rstn externally forced low, falling edge event. the reason is to have the same situation of the reset source code after a power-on reset and an external reset as an emulator usually starts with a system reset. so during development of the UJA1061 software with an emulator, the UJA1061 will usually start-up with an external reset. if the emulator is not used, the software starts-up with the power-on code. since the power-on code is a separate bit (pwons; power-on status) in the system status register the microcontroller can distinguish between the power-on reset and the external reset. the UJA1061 will be reset actively if pin rstn is pulled low from external circuitry. the UJA1061 will lengthen any reset event to 1 or 20 ms in order to make sure that external hardware is reset properly. after the first battery connection, a long power-on reset of 20 ms is provided after voltage v1 is present. when started, the microcontroller can set the reset length control (rlc) flag within the UJA1061; this allows the reset pulse to be shortened to 1 ms for future reset events. with this flag set, all reset events are shortened to 1 ms. due to fail-safe behaviour, this flag will be reset automatically (to the longer one) within restart mode, the first battery connection or with an externally-applied falling edge at pin rstn. with this mechanism it is guaranteed that an erroneously-shortened reset pulse will restart any microcontroller at least within the second trial using the long reset pulse. the behaviour of pin rstn is shown in fig.7. the duration of t rstl depends on the setting of the rlc flag (defining the reset length). once an external reset event has occurred the system controller enters start-up mode. now the watchdog starts monitoring pin rstn to check whether it is clamped or chattering. finally fail-safe mode is entered in case pin rstn is not properly released. the reset state diagram is given in fig.8. if pin rstn is released by the UJA1061 and the externally lengthening is shorter than 256 ms, the watchdog initialization starts with a time-out of 256 ms (start-up time). if the watchdog initialization has been successful within this start-up time, normal or flash mode will be entered. if the start-up time expires, restart mode is entered providing a long reset pulse and resetting the v1 undervoltage threshold to the high level. now with a second system start and another 256 ms start-up time it is possible to enter normal mode. if this fails again, fail-safe mode is entered. furthermore, pin rstn is monitored for a continuously low clamping situation. once the UJA1061 pulls pin rstn high but pin rstn level remains low for more than 256 ms, the UJA1061 immediately enters fail-safe mode since this points to an application failure.
2004 mar 22 18 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 in order to prevent a continuously running microcontroller, the UJA1061 also detects high-level clamping at pin rstn. if the high-level remains on the pin for more than 128 ms while pin rstn is driven internally to a low level by the UJA1061, the UJA1061 falls back immediately to fail-safe mode since the microcontroller cannot be reset any more. by entering fail-safe mode, the v1 voltage regulator shuts down and the microcontroller stops. additionally, chattering reset signals are handled by the UJA1061 in such a way that the system safely falls back to fail-safe mode with lowest power consumption. externally applied reset signals force a mode change of the UJA1061 only within normal, standby and flash mode. within start-up, restart and fail-safe mode, any externally applied reset signals are only monitored by the UJA1061 for clamping situations. in this way, no deadlock of the system is possible in the case of the reset line being affected by external disturbances. handbook, full pagewidth v rstn v rv1 v rv2 power-up power- down under- voltage missing watchdog access under- voltage spike v1 time time v uh : release level v ul : detection level mce628 t rstl t rstl t rstl fig.7 reset pin behaviour.
2004 mar 22 19 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 mce629 set reset low event action set reset high (pin rstn = low) < 256 ms t > t (reset mode) (1 ms or 20 ms) pin rstn = high normal reset mode: 1 ms or 20 ms start-up watchdog init ok t < 256 ms set reset low set reset high (pin rstn = low) < 256 ms t > t (reset mode) (here always 20 ms) pin rstn = high (pin rstn = low) 3 256 ms fail-safe reset mode: 20 ms restart wait watchdog init wait watchdog init t > 256 ms and no undervoltage v1 t > 256 ms or undervoltage v1 oscillator fail (pin rstn = high and rstn driven low) > 128 ms watchdog too early/time-out or interrupt ignored > 256 ms or wake-up event or v1 active and v1 undervoltage or v1 current monitor or (v3 overload and sleep mode) or wrong mode register code or flash entry enabled reset mode: no change reset threshold: no change (pin rstn = low) 3 256 ms set reset mode: 20 ms set reset threshold: high t > 256 ms set reset mode: 20 ms set reset threshold: high watchdog init ok power-on reset mode: 20 ms reset threshold: high rstn externally forced falling edge fig.8 reset state description.
2004 mar 22 20 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.5.2 e nable output pin en the functionality of the pin en is almost identical to that of pin rstn. the differences are: output functionality only, not an input/output en output can only be released by the microcontroller via an spi access. pin en, active low, is used for emergency shut-down of items such as external power components. during all reset events when pin rstn is pulled low the en control bit will be reset, pin en will be pulled low and will stay low after pin rstn is released, within the normal mode and flash mode of the UJA1061, the microcontroller can set the en control bit via spi again. this results in releasing pin en which then returns to high-level. based on this, the en signal also can be used as a general purpose output when the system is running properly. 6.6 power supplies 6.6.1 s upported battery systems besides the bat14 supply pin (14 v), which is used to supply voltage regulators v1 and v2, the UJA1061 provides a bat42 supply pin (42 v) in order to support 42 v systems. the UJA1061 supports three power supply architectures: single 42 v battery system C pin bat42 has to be connected to the 42 v battery C pin bat14 has to be connected to, for example, a dc/dc converter (42 to 14 v or lower) single 14 v battery system C both pins bat14 and bat42 have to be connected to the 14 v battery two batteries (14 and 42 v) system C bat42 has to be connected to the 42 v battery C bat14 has to be connected to the 14 v battery. to be able to control the external dc/dc converter for a single 42 v architecture or for connecting pin bat 14 to a voltage lower than 12 v (in order to achieve a higher output current source capability of v1), sysinh is high when v1 and/or v2 is present, and is floating in all other cases. in sleep mode the sysinh signal allows the external dc/dc converter to be disabled if both voltage supply outputs v1 and v2 are no longer needed. in this case the UJA1061 is powered only via pin bat42 and pin sysinh will float. in this situation, no input voltage is required at pin bat14. whenever v1 and/or v2 is needed for the application, pin sysinh will be set high again, providing the bat42 voltage to the external dc/dc converter or any other dedicated hardware. 6.6.2 s tatic and dynamic battery monitoring static battery monitoring is available at pin bat42. with prolonged low voltages on pin bat42, the UJA1061 forces a system reset and sets a dedicated power-on reset flag in the reset source code register. fail-safe mode will be entered, even if bat14 is still connected. the UJA1061 has a dedicated sense pin for dynamic monitoring the battery contact of an electronic control unit. as this sense pin is connected at the electronic control unit input before the connection to the external reverse current protection diode for pin bat42, a fast detection of a power-down, e.g. caused by a loose battery connector, can be executed. the advantage is in the extra time for the microcontroller to shut down properly before a system reset occurs as a result of an undervoltage at v1. 6.6.3 v oltage regulators v1 and v2 the UJA1061 has two independent voltage regulators that are supplied through the external bat14 input pin. one regulator (v1) is for the microcontroller and one regulator (v2) is for the fault tolerant can-transceiver. this dual regulator concept offers the following advantages: all noise coming from the microcontroller load is decoupled from the bus lines the UJA1061 can always support the complete fault-tolerant physical layer, including the biasing, even if the microcontroller is not present (v1 short-circuited or load is too high) the possibility of choosing a supply voltage for the microcontroller that is lower than 5,v, i.e. 3.3, 3 or 2.5 v according to version. 6.6.3.1 v1 voltage regulator the v1 voltage regulator is targeted to supply the application microcontroller. as well as this primary function, the accuracy of this regulator makes it suitable to supply the reference voltage for the analog-to-digital converter of the microcontroller. v1 voltage is monitored continuously in order to provide the system reset signal when undervoltage situations occur. whenever v1 voltage falls below one of the two programmable thresholds, a hardware reset will be forced.
2004 mar 22 21 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 the ram status monitor monitors the v1 voltage. if v1 voltage is lower than the minimum voltage needed for the microcontroller ram while v1 is active, then the corresponding spi bit will be set. this bit can be read by the microcontroller when v1 has recovered (no reset is generated). depending on the version-dependent output voltage of v1, the undervoltage reset threshold as well as the ram status monitor threshold are adapted accordingly. the v1 regulator is protected against overload. the maximum output current allowed at pin v1 depends on the input voltage connected to pin bat14. the closer the input voltage comes to the v1 output voltage, the more output current can be sourced by the regulator. this feature is very useful in combination with an external dc/dc converter in providing a bat14 voltage close to v1 (7 v, for example). 6.6.3.2 v2 voltage regulator the second independent voltage regulator v2 provides a 5 v supply for the can transmitter. the pin v2 is intended for the connection of external buffering capacitors. v2 is controlled autonomously by the can physical layer and is activated upon any detected can-bus activity, or is activated if the can physical layer is enabled by the application microcontroller. this supply is short-circuit protected and will be disabled in case of an overload situation. the status of v2 will be reflected to the application via dedicated interrupt and status flags. 6.6.4 s witched battery output (v3) v3 is a high-side switched bat42-related output to drive external loads such as wake-up switches or relays. the features of v3 are as follows: supports three application controlled modes of operation; on, off or cyclic mode two different cyclic modes allow the supply of external wake-up switches; these switches are powered intermittently (for 384 m s every 16 ms or for 384 m s every 32 ms) thus reducing the systems power consumption in case a switch is continuously active; the wake-up input of the UJA1061 is synchronized with the v3 cycle time. the switch is protected against short-circuits to ground and current overloads. in case regulator v3 is overloaded, pin v3 is automatically disabled, the corresponding mode bit is reset and an interrupt is forced, if enabled. if the UJA1061 was in sleep mode (v1 off), a wake-up is forced and the corresponding reset source code becomes available within the reset source register; this signals to the application that the wake-up source via v3-supplied wake-up switches has been lost. 6.7 can transceiver the integrated fault-tolerant can transceiver of the UJA1061 is an advanced iso11898-3 compliant version of the tja1054/tja1054a and is fully inter-operable with these two stand-alone transceivers. the improvements and extensions of the integrated fault-tolerant can transceiver-cell compared with the tja1054/tja1054a are the following: enhanced error signalling; all bus failures are separately forwarded to the spi register handling and reporting of clamping situations on can and rxd/txd interface ground shift detection with two selectable warning levels to detect possible local gnd problems before the can communication is affected supports selective sleep mode with global wake-up message filter improved wake-up filtering for canl no recovery of bus failures during mode changes between normal mode or low power modes 42 v system support for canl low power termination. 6.7.1 m ode control different to existing stand-alone fault-tolerant can transceivers, the integrated autonomous controller defines the mode of the can transceiver. this implies that the fault-tolerant can transceiver, which is supplied by its dedicated v2 supply, supports the bus failure management and bus levels in all modes and independently from the microcontroller. this ensures that even a failing microcontroller (or failing v1 supply) does not influence the communication of the rest of the can network. furthermore fail-safe behaviour is guaranteed in all modes to protect the system against unwanted power consumption. the controller of the can physical layer provides two major modes of operation of the can transceiver, the active mode and the auto mode (see fig.9). two dedicated can status bits (canmd) are available to indicate to the application whether the transceiver is in normal, on-line, selective sleep or off-line mode.
2004 mar 22 22 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 mce630 on-line v2: on/off (v2d) transmitter: off receiver: on/lp (v2d) pin rxdc: wake-up flip flop canl bias: v2/ floating/(v2d) active v2: on/off (v2d) transmitter: on/off (ctc) receiver: on/lp (v2d) pin rxdc: bitstream/high (v2d) canl bias: v2/ floating/(v2d) off-line v2: off transmitter: off receiver: lp pin rxdc: v1 canl bias: lp/ floating/(v2d) selective sleep v2: on/off (v2d) transmitter: off receiver: on/lp (v2d) pin rxdc: v1 canl bias: v2/ floating/(v2d) event action power-on global wake-up can message detected wake-up flip flop set cpnc set to logic 0 cm = logic 0 and cpnc = logic 0 cm = logic 1 cpnc set to logic 0 can mode = logic 0 and cpnc = logic 1 cm = logic 1 wake-up flip flop cleared cm = logic 1 cpnc set to logic 0 can wake-up filter passed and cpnc = logic 0 wake-up flip flop set can wake-up filter passed wake-up flip flop set cpnc = logic 1 wake-up flip flop cleared cpnc set to logic 0 no activity t > t off-line wake-up flip flop cleared no activity t > t off-line active can mode = logic 1 auto can mode = logic 0 can wake-up filter passed and cpnc = logic 1 fig.9 states of the can transceiver.
2004 mar 22 23 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.7.1.1 active mode within the active mode the can transceiver operates as in the normal mode of the tja1054. here normal communication is possible with pin canl terminated at the voltage rail v2 (5 v). the active mode can be entered only using the can mode bit if the system controller is within its normal mode or in flash mode. transmission and reception of messages is possible in the active mode. if the regulator v2 is not able to start within the v2 clamped low time (>t v2(clt) ) or a short-circuit has been detected during an already activated v2, regulator v2 becomes disabled (v2d will be reset) and an interrupt is forced to the microcontroller, if enabled. the corresponding fail flag will be set at the same time; also the transmitter and receiver are switched off and any transmission of messages is blocked by the UJA1061. the termination of canh and canl will be set to floating. if the microcontroller wants to transmit again, it can activate the transmitter, the corresponding termination and the receiver again by a falling edge of the can transmitter control (ctc) bit. if this continues to fail (v2 cannot start; v2d will be reset) an interrupt is forced again (if enabled) and v2, the transmitter, the receiver and the termination will be switched off again. this makes sure that a short-circuited v2 does not result in high power consumption. a can transmitter off bit is available to set the can transceiver to a listen-only mode. in this mode the transmitter output stage is disabled. within active mode, a wake-up via can will never result in a reset. 6.7.1.2 auto mode the auto mode is entered if the can mode bit is cleared. from now on no active transmission is possible. the transmitter will be switched off. the auto mode is also entered whenever the system controller leaves its normal mode. this clears the can mode bit automatically. within auto mode the physical medium is still supported (on-line and selective sleep mode) including the bus failure management as long as there is some activity on the bus lines. canl continues to be terminated strongly towards v2 and v2 is active. once the bus becomes recessive or dominant for a certain time (t offline ) the transceiver goes to off-line. the off-line timer is programmable in two steps with the can off-line timer control (cotc) bit. entering off-line will set the timer to the longest period independently of the cotc bit and will be reset with every can wake-up event three different states are implemented: on-line selective sleep off-line. 6.7.1.3 on-line on-line will be entered after the UJA1061 has detected some activity on canl and/or canh, while the transceiver was off-line and the can partial networking control (cpnc) bit was low. a can message containing a dominant phase, followed by a recessive phase and followed again by a dominant phase, results in a wake-up of the UJA1061, after having passed the can wake-up filter. pin rxdc is forced low upon wake-up towards on-line and keeps low until the can mode bit is set (active mode) or the cpnc bit is set to logic 1, entering selective sleep. additionally a reset or interrupt is forced, if programmed accordingly. on-line also can be entered by resetting the can mode bit, cm (auto mode) during normal mode of the UJA1061 with the cpnc bit set to low. after some bus activity, the wake-up flip flop will be set again, together with a low signal on rxdc. if the bus stays continuously dominant or recessive for the off-line time (t offline ), off-line will be entered, clearing the wake-up flip flop. leaving on-line, the wake-up flip flop will be cleared in order to be ready for the next wake-up event. 6.7.1.4 selective sleep selective sleep is selectable with the can partial networking control (cpnc) bit. in contrast with on-line, in selective sleep any wake-up, with the exception of the global wake-up can message, due to can-bus activity is ignored but the physical medium, including bus failure management and strong termination, continues to be supported in order to support partial networking. in this mode, rxdc stays continuously at v1 level.
2004 mar 22 24 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 entering selective sleep out of off-line is possible when the can wake-up filter has been passed and the cpnc bit has been set previously to logic 1. in contrast with entering on-line out of off-line, the wake-up flag is not set, so not resulting in any activity of v1 and the microcontroller. selective sleep mode will also be entered out of on-line in case bit cpnc becomes logic 1. if the wake-up flag was set, it will be cleared. another possibility for entering selective sleep mode is resetting the cm bit in active mode with bit cpnc set logic 1. if the can-bus has been dominant or recessive continuously for the off-line time (t offline ), off-line will be entered. the second possibility to leave selective sleep and enter active mode is by software control, possible by setting the can mode bit logic 1. a third possibility to leave selective sleep is by entering on-line, possible only after detection of a dedicated global wake-up can message. this comprises two messages using any can identifier but a dedicated data pattern, first the can wake-up message pattern and second the confirmation message pattern: can wake-up message: 0xc6 ee ee ee ee ee ee ef confirmation message: 0xc6 ee ee ee ee ee ee 37. there may be any other can message frame between the two message patterns. the maximum message separation time period has to be less than t timeout . if selective sleep was entered out of off-line due to bus activity, the message separation timer will start directly without waiting for the first wake-up message data pattern. the confirmation message data pattern, received before the overflow of the timer, is then sufficient to go to on-line. whenever selective sleep is left, the selective sleep control bit is cleared again automatically. within sleep mode, any wake-up event is automatically forwarded to the system reset due to power-up on v1. 6.7.1.5 off-line within off-line the can physical layer becomes automatically terminated towards an internal power supply, supplied out of bat42. v2 is disabled in order to save supply current. any can wake-up event automatically restarts v2, entering on-line or selective sleep. wake-up is signalled via rxdc (low) and rstn (low) or intn (low) if programmed accordingly. in on-line, pin rxdc is held low until the can mode bit is set successfully, or the can physical layer enters selective sleep by setting the cpnc bit logic 1. once the bus becomes recessive or dominant for a certain time (t offline ) the transceiver enters off-line. the off-line timer is programmable in two steps with the can off-line timer control (cotc) bit. entering off-line will set the timer to the longest period independently of the cotc bit and will be reset with every can wake-up event 6.7.2 t ermination control in active mode, on-line and selective sleep, rth and rtl are strongly terminated to ground and to v2 respectively. the normal bus-failure management (bfm) (known from the tja1054/tja1054a) is active. during short-circuits at canl and/or canh, the corresponding rtl or rth pin becomes floating. when v2 is off or unstable, both pins become floating and the normal bfm is left. a floating sysinh results immediately in a switch-over towards floating rth and rtl and skipping the normal bfm because v2 level soon can fall. 6.7.3 b us , rxd and txd failure detection the UJA1061 can distinguish between bus, rxd and txd failures as indicated in table 1. all failures will be signalled separately to a 4-bit register. any change (detection and recovery) will give an interrupt to the microcontroller, if enabled (limited to only one interrupt per watchdog period). polling of the spi register is always possible. 6.7.3.1 gnd shift detection two different gnd shift levels can be detected, programmable by the microcontroller. any detected or recovered gnd shift event results in an interrupt of the microcontroller, if enabled (limited to only one interrupt per watchdog period).
2004 mar 22 25 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 table 1 can-bus, rxd and txd failure detection note 1. canl stays active with weak short-circuits to bat due to wake-up requirements within large networks. failure description driver and biasing circuit disabling hxvcc canh to v cc (5 v) short-circuit canh off, weak rth hxbat canh to bat (14 and 42 v) short-circuit canh off, weak rth hxgnd canh to gnd short-circuit none lxbat canl to bat (14 and 42 v) short-circuit canl off, weak rtl; note 1 lxgnd canl to gnd short-circuit canl off, weak rtl lxvcc canl to v cc (5 v) short-circuit none hxl canh to canl short-circuit canl off, weak rtl h// canh interrupted none l// canl interrupted none bus dom bus is continuously clamped dominant (double failure); even within single-wire mode the receiver remains dominant canl off, weak rtl bus rec bus is continuously clamped recessive (double failure); driving messages to the bus is not possible even while the driver is active none txdc dom pin txdc is continuously clamped dominant (handles also rxdc to txdc short-circuits) transmitter disabled but no change in biasing rxdc rec pin rxdc is continuously clamped recessive transmitter disabled but no change in biasing rxdc dom pin rxdc is continuously clamped dominant none
2004 mar 22 26 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.8 lin transceiver the integrated lin transceiver of the UJA1061 has the following features: lin specification revision 2.0 compatible 42 v system handling compatibility disabling of the termination switch during a short-circuit from lin to gnd no reverse currents are possible from rtlin to the battery supports two different lin-recessive levels; related to bat42 or to bat14. the master and slave termination can be connected externally between pins lin and rtlin. 6.8.1 m ode control the first state of the lin transceiver following power-on is off-line (see fig.10). the transmitter and receiver both consume no current but wake-up events will be recognised by the separate wake-up receiver. pin rxdl reflects the status of the wake-up flip flop: high after power-on; low after a wake-up event via the lin-bus. any lin event with a dominant lin level longer than the specified wake-up time (t bus(lin) ) followed by a recessive level will wake-up the UJA1061, resulting in a low signal at pin rxdl and, if enabled, a low signal at pin rstn or at pin intn. when the UJA1061 enters normal or flash mode, the lin transceiver automatically enters on-line and the wake-up flip flop will be cleared. the wake-up flip flop will be cleared also when the UJA1061 falls into fail-safe mode as the result of a microcontroller wake-up failure. a remote lin wake-up out of standby or flash mode will wake-up the system via a dedicated hardware reset or via an interrupt, depending on the lin interrupt enable (linie) bit. with bit linie set to logic 1, pin intn remains low until the interrupt register has been read and cleared. a remote lin wake-up out of sleep or fail-safe mode always happens with a reset independent of the programming due to the unpowered situation of the microcontroller. the differences between on-line and off-line are as follows: off-line. the transmitter is always off and pin rxdl continuously reflects the wake-up event at the lin-bus on-line. the status of the transmitter is software controlled by the microcontroller via the lin transmitter control bit (ltc) while pin rxdl reflects the data bit stream on the lin-bus bit l42 determines whether the pin rtlin is supplied by the bat14 voltage source or by an internal 12 v supply generated from the bat42 regulator, in order to support the future 42 v lin standard. pin rtlin has to be applied via a buffer capacitor in case bit l42 is set. default operating mode is bat14 related. during on-line, with no short-circuit between the lin bus and gnd, pin rtlin provides an internal switch to select bat14 or the internal 12 v voltage, depending on the l42 bit. for master and slave operation an external resistor, respectively 1 k w or 30 k w , can be applied between pins rtlin and lin. an external diode in series with the termination resistor is not needed because an internal diode is incorporated. if the lin wire becomes short-circuited to gnd, pin rtlin will switch to a current source of approximately 75 m a to prevent significant battery discharge (some current is needed for failure recovery). a recessive level on the lin wire activates the normal termination again. the 75 m a current source is also present in off-line with no clamped dominant lin-bus. pin rtlin floats in off-line in case there is a short-circuit to gnd. entering active mode out of off-line always results in switching on the strong switch at pin rtlin, independent of a previously detected short-circuit on lin to ground. if the short-circuit still exists, the switch will be substituted by the 75 m a current source after the dominant time-out at pin lin. the different states of pin rtlin are shown in fig.11. the receiver comparator levels are battery related to bat14 in a 14 v system with the l42 bit cleared, and related to the internal 12 v voltage supply in 42 v systems with the l42 bit set.
2004 mar 22 27 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 mce631 active transmitter: on/off receiver: on termination: on/75 m a pin rxdl: bitstream off-line transmitter: off receiver: wake-up termination: 75 m a/ floating pin rxdl: wake-up flip flop event action power-on UJA1061 enters normal or flash mode wake-up flip flop cleared UJA1061 enters standby, start-up, restart or fail-safe mode UJA1061 enters fail-safe mode wake-up flip flop cleared fig.10 states lin transceiver. mce632 rtlin = off rtlin = on supplied by bat14 or fixed 12 v 5 % rtlin = 75 m a supplied by bat14 or fixed 12 v 25 % power-on non-active mode and receiver = rec for t > t lin(rec) mode change to active mode active mode and receiver = dom for t > t lin(dom) or non-active mode active mode and receiver = rec for t > t lin(rec) or mode change to active mode non-active mode and receiver = dom for t > t lin(dom) fig.11 states of the rtlin pin.
2004 mar 22 28 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.8.2 b us and txdl failure detection the UJA1061 handles and signals the following lin-bus related failures: lin-bus clamped dominant; within active mode the termination switch at pin rtlin is switched to the internal weak current source; within off-line rtlin will be floating txdl clamped dominant; the transmitter is disabled lin-bus clamped recessive; the transmitter is switched off and the lin transmitter off bit (lto) is set. these failure events force an interrupt to the microcontroller whenever the status changes and the corresponding interrupt is enabled. 6.9 inhibit output (pin inh) the inh output pin, which can be used as inhibit for an extra (external) voltage regulator, is floating after the first powering of the UJA1061. this ensures that yet-to-be connected voltage regulators are switched off. the inh bit in the corresponding spi register can be accessed in normal mode, flash mode and in standby mode. whenever restart, sleep or fail-safe mode is entered, the inh bits are reset again, with pin inh floating as the result. this is also true whenever undervoltage of v1 has been detected, or an external reset edge is applied to the UJA1061. therefore, the application has to reactivate external supplies in a failure situation or in the event of an external reset. the inh output pin can also be programmed as limp home output, which is also floating after power-up but is activated by the UJA1061 in case the UJA1061 enters fail-safe mode. for fail-safe reasons, this limp home behaviour of pin inh can be activated by setting the limp home mode (lhm) bit via the special mode register. this lhm bit can therefore be set only once after a first battery connection before the watchdog is initialized, that is within the 256 ms start-up period and before the first spi write access to any other register. 6.10 wake-up input (pin wake) the behaviour of pin wake depends on the sampled level: a pull-down behaviour is activated when the pin is pulled low, and a pull-up behaviour towards bat42 is activated when the pin is pulled high externally. the setting of the wake sample control bit (wsc) defines the sample mode of the pin: continuous sampling (with an internal clock) if the bit is set logic 1 sampling synchronised to the cyclic behaviour of v3 if the bit is set logic 0 (see fig.12). this is to save bias current within external switches in low-power operation. two repetition times are possible: 16 and 32 ms. if v3 is continuously on, pin wake input will be sampled continuously also, regardless of the level of the bit wsc. if the interrupt mode is selected, a negative edge on pin wake sets pin intn immediately to low. reading the corresponding interrupt register clears all bits. if the reset mode is selected, the wake-up event forces a hardware reset without interrupt. the reset source bits in the system status register reflect the source of the reset event, while dedicated status bits, edge wake status (ews) and level wake status (lws), within the same register, offer information according the actual status of pin wake. these two bits can be polled and read out also when the interrupt option instead of the reset option has been chosen.
2004 mar 22 29 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 v wake sample active v 3 flip flop v intm mce633 t w(cs) = 384 m s t on(cs) = 16 or 32 ms t su(cs) = 256 m s approx. 70 % button pushed button released signal remains low due to biasing (history) signal already high due to biasing (history) fig.12 pin wake, cyclic sampling via v3. 6.11 interrupt output in order to support multiple interrupt sources within a system, pin intn provides an open-drain output configuration. whenever at least one bit is set within the interrupt register this pin is forced low. reading the interrupt register clears all set bits. only these bits are cleared as they have definitely been read during that access. the interrupt register will be cleared also during a system reset (rstn low). 6.12 temperature protection the temperature of the UJA1061 chip is monitored as long as the microcontroller voltage regulator v1 is active. to avoid any unexpected shut-down of the application by the UJA1061, the temperature protection will not switch off any part of the UJA1061 or activate a defined system stop of its own accord. a too-high temperature only generates an interrupt to the microcontroller, if enabled, and the corresponding status bit is set. the microcontroller can now decide whether to switch off parts of the UJA1061 in order to decrease the chip temperature. 6.13 spi interface the serial peripheral interface (spi) provides the communication link with the microcontroller and supports multi-slave and multi-master operation. the spi is configured for full duplex data transfer; while new control data is shifted-in, status information is automatically returned. all registers provide a read-only access option. thus all status bits can be read back by the application at any time. the spi interface with a data rate up to 2 mbit/s provides four interface signals, including chip select (see fig.13). any bit-sampling is performed with the falling clock edge and the data is shifted with the rising clock edge. all spi interface signals are derived from v1 in order to avoid problems with reversed supplies. most of the registers are only accessible (read and/or write) during normal mode or standby mode. some other registers, needed for watchdog initialization and entering special modes, are only accessible during the start-up and/or restart mode.
2004 mar 22 30 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 the following spi interface signals are implemented: scs - spi chip select; active low sck - spi clock; default level is low due to low-power concept sdi - spi data input sdo - spi data output; floating when pin scs is high. the spi interface can be accessed only when pin rstn (input channel of rstn) is set high. possible spi failures are: spi clock count failure (wrong number of clock cycles during one spi access). within one scs cycle only 16 clock periods are allowed. any deviation from the 16 clock cycles results in an spi failure interrupt, if enabled. the access is ignored by the UJA1061. in start-up and restart mode, a reset is forced instead of an interrupt wrong mode register code. the following events result in an immediate system reset without interrupt according to the state diagram of the system controller C mode other than initializing normal mode selected within mode register in start-up or restart mode C initializing flash mode outside of start-up mode or within start-up mode without previous flash sequence C bit wdd set in the mode register; this bit may only be set via the special mode register C illegal watchdog period coding, see section 6.14.2. illegal mode register code during normal or standby mode of the UJA1061. with a read-only access to the system status register or the system diagnosis register which, with the mode register, share the same spi address, the data written to the mode register is dont care and is ignored. reading these two system registers is allowed at any time independent of watchdog window cycles. handbook, full pagewidth scs sck 01 sampled floating floating mce634 x x msb 14 13 12 01 lsb msb 14 13 12 01 lsb x sdi sdo 02 03 04 15 16 fig.13 spi timing protocol.
2004 mar 22 31 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14 spi register mapping any control bit which might be set in software is readable by the application. this allows software debugging as well as control algorithms to be implemented. there is also a read-only access possible without actively writing to an spi register. the following constraints are implemented in the register mapping: the number of clock cycles during one spi access has to be 16 watchdog period and mode setting is performed within the same access cycle; this allows a mode change of the UJA1061 with simultaneously changing the period and the mode of the watchdog each register carries only 12 functional bits; 4 bits are used for register selection and read/write definition. 6.14.1 r egister overview since the spi interface is bidirectional, each write access automatically implies a register read access to one of the internal registers, see table 2. in order to allow a register to be read without writing data to it, a read-only feature is incorporated. a 4-bit header defines any spi access to one of the registers. the first two bits, address bits a1 and a0, define the register address. these are followed by the read register select bit rrs that defines the feedback register for this access. the fourth bit ro allows a read only access to one of the feedback registers. depending on the mode, some registers can be written to and/or read from, and some not. during the first watchdog initialization phase, directly after the first battery connection, the special mode bits register can be set only once. after this special mode register access, or any other access to the UJA1061, these bits cannot be accessed again. this special mode register is used for entering the software development mode. the software development mode bit sdm, present in the system configuration register, can be read out and also reset all the time in normal operating mode and standby mode. the UJA1061 has two 12-bit general purpose registers with no prescribed bit definition. during power-up the bits of general purpose register 0 (gp0) will be loaded with a device identification code consisting of the sbc type and sbc version. the bits of general purpose register 1 (gp1) will be reset after power-up. all bits of gp0 and gp1 cannot be changed any more by the UJA1061, with the exception of bit 11 of register gp0 which indicates whether the content of register gp0 is the device identification code (bit 11 = logic 1), or used already as an extra register by the microcontroller (bit 11 = logic 0). only the application microcontroller can change the other 23 bits during the start-up mode, restart mode or flash programming mode. the microcontroller can read these two registers all the time. the purpose of the general purpose register is to give the microcontroller the possibility of storing certain system status information that cannot be held within the microcontroller memory. this is very useful for applications making use of the sleep mode (unpowered microcontroller) saving important data bits for the next operating cycle. furthermore these two registers can be used for enhanced system diagnosis and fail-safe features. if, for example, a fault in the memory of the microcontroller always causes the same reset due to a software crash, the microcontroller can count these events and write the corresponding information into these register bits. the reset source register bits offer the corresponding information about the root cause of the problem. thus, the microcontroller can take action depending on the number of identical resets and so prevent an ecu from permanent system crash situations consuming permanently high power. thus, the general purpose registers offer a kind of non volatile memory to the microcontroller since the UJA1061 is always powered from the battery line, independently from the supply of the microcontroller which could possibly be without power from time to time.
2004 mar 22 32 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 table 2 register overview address (binary bits 15, 14) mode write access name read access read register select bit (rrs) = 0 name read register select bit (rrs) = 1 name 00 all mode register mod system status register stat system diagnosis register diag 01 normal operating mode; standby mode interrupt enable register ie interrupt enable feedback register ief interrupt register int start-up mode due to power-on special mode register spe start-up mode; no power on; restart mode; flash programming mode no write access possible - 10 normal operating mode; standby mode system con?guration register sc system con?guration feedback register scf general purpose feedback register 0 gpf0 start-up mode; restart mode; flash programming mode general purpose register 0 gp0 11 normal operating model; standby mode physical layer control register plc physical layer control feedback register plcf general purpose feedback register 1 gpf1 start-up; mode restart mode; flash programming mode general purpose register 1 gp1
2004 mar 22 33 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.2 m ode register the mode register has cyclic access during system operation. here the watchdog is defined and re-triggered as well as the current mode of operation is selected. furthermore the global enable output (bit en) as well as the software development mode (bit sdm) control bit are defined here. depending on the system requirements, the can physical medium can be activated with any access to the can mode bit (cm). this register has to be written during system start-up within 256 ms after rstn has become released (high-level on rstn). any write access is checked for proper watchdog and system mode coding. if an illegal code is detected, this access is ignored by the UJA1061 and a system reset is forced according to the state diagram of the system controller. table 3 mod - mode register (address 00) bit description bit symbol description value function 15, 14 a1, a0 register address 00 select mode register 13 rrs read register select 1 read system diagnosis register (diag) 0 read system status register (stat) 12 ro read only 1 read selected register without writing to mode register 0 read selected register and write to mode register 11 to 6 nwp[5:0] nominal watchdog period normal operating mode (ms) standby mode (ms) flash programming mode (ms) sleep mode (ms) 001001 4 20 20 160 001100 8 40 40 320 010010 16 80 80 640 010100 32 160 160 1024 011011 40 320 320 2048 100100 48 640 640 3072 101101 56 1024 1024 4096 110011 64 2048 2048 6144 110101 72 4096 4096 8192 110110 80 off (1) 8192 off (1) 5 to 3 om[2:0] operating mode 001 normal operating mode 010 standby mode 100 sleep mode 101 initializing normal mode 111 flash programming mode; note 2 011 initializing flash mode 1; note 3 2 sdm software development mode (4) 1 no watchdog reset; no interrupt monitoring; no reset monitoring; no transitions to fail-safe mode; fail-safe is entered only with a v1-undervoltage condition longer than 256 ms 0 normal watchdog, interrupt, reset monitoring and fail-safe behaviour
2004 mar 22 34 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 notes 1. if the watchdog is triggered with the watchdog off code while the UJA1061 is in standby mode or while the UJA1061 enters standby mode, the v1 current monitoring function stays disabled for a period of time equal to the previous or the default (4096 ms) watchdog period. the default period is selected if the standby mode is entered directly with watchdog off mode. after that period, the current monitoring is enabled. then the behaviour of the UJA1061 upon a too-high v1 current depends on the setting of the v1cmc bit within the system configuration register. if this bit is set (reset option), a too-high v1 current causes an immediate reset. if this bit is not set (watchdog restart option), the watchdog starts a new period without the possibility to be disabled except by being triggered again with the watchdog off code. if the watchdog off code is chosen, the watchdog time-out interrupt has no function. 2. the flash programming mode can be entered only with the consecutive watchdog service sequence normal operating mode/flash programming mode/normal operating mode/flash programming mode using multiple watchdog period times because access to this register is allowed only while the watchdog is open for write access. now the UJA1061 forces a system reset and enters start-up mode in order to prepare the microcontroller for flash memory download. also the software has to use the initializing flash mode within 256 ms in order to enter the flash programming mode of the UJA1061 successfully. 3. the watchdog is immediately disabled entering sleep mode with watchdog off behaviour selected because pin rstn is pulled low immediately with the mode change. 4. setting of bit sdm is possible only via the special mode register and only once after supplying the UJA1061 the first time with bat42 voltage. access of the special mode register has to be executed before the watchdog is initialized, that is, before the first write to the mode register. resetting is possible at any time via the mode register. a set sdm flag disables all reset events caused by the UJA1061 during normal operating mode (except for wrong mode register code resets), disables the interrupt time monitoring function during normal operating mode, the watchdog initialization time, the reset monitoring and the transitions to fail-safe mode with the exception of a v1-undervoltage longer than 256 ms. this bit is set automatically if pin test is forced to 7 v or higher during power-on of the UJA1061 (software development mode or forced normal mode). watchdog trigger failures resulting only in the interrupt if enabled in the interrupt enable register. 1 en enable 1 en output pin high 0 en output pin low 0 cm can mode 1 active mode selected; can active; transmissions possible 0 auto mode selected; can is allowed to fall into low power bit symbol description value function
2004 mar 22 35 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.3 s ystem status register this register allows status information to be read-back from the UJA1061. table 4 stat - system status register (address 00) bit description bit symbol description value function 15, 14 a1, a0 register address 00 read system status register (stat) 13 rrs read register select 0 12 ro read only 1 read system status register without writing to mode register 0 read system status register and write to mode register 11 to 8 rss[3:0] reset source (1) 0000 power-on reset; ?rst connection of bat42 or bat42 below power-on voltage threshold or rstn was forced low externally 0001 cyclic wake-up out of sleep mode 0010 low v1 supply; v1 has dropped below the reset threshold 0011 v1 current above threshold within standby mode of the UJA1061 while watchdog off behaviour was selected and the reset option is selected within the system con?guration register 0100 v3 voltage is down due to short-circuit occurring during sleep mode 0101 reserved 0110 UJA1061 ready to enter flash programming mode 0111 wake-up event via can while reset behaviour selected or during sleep mode 1000 wake-up event via lin while reset behaviour selected or during sleep mode 1001 wake-up event via wake while reset behaviour selected or during sleep mode 1010 wake-up event out of fail-safe mode 1011 watchdog over?ow (normal operating mode)/time-out (standby mode/flash mode); trigger too late 1100 watchdog not initialized in time; 256 ms exceeded 1101 watchdog triggered too early; window missed 1110 illegal mode register code 1111 interrupt not served in time (within 256 ms) 7 - reserved 0 reserved for future use; in order to stay compatible with future silicon versions using this bit, software should ignore this bit value 6 lws level wake status 1 pin wake is above the threshold 0 pin wake is below the threshold 5 - reserved 0 reserved for future use; in order to stay compatible with future silicon versions using this bit, software should ignore this bit value
2004 mar 22 36 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 note 1. the reset source register is updated with each reset event and not cleared. the last reset event is captured. 4 ews edge wake status 1 pin wake negative edge event detected; cleared upon read 0 pin wake no edge detected 3 tws temperature warning status 1 chip temperature exceeds the warning limit 0 chip temperature is below the warning limit 2 sdms software development mode status 1 no watchdog reset; no interrupt monitoring; no reset monitoring; no transitions to fail-safe mode; only during a v1 undervoltage longer than 256 ms 0 normal watchdog interrupt, reset monitoring and fail-safe behaviour 1 en enable status 1 pin en output activated, a (v1-related) high level is driven 0 pin en output released a low level is driven 0 pwons power-on reset status 1 power-on reset; ?rst connection of bat42 or bat42 below power-on voltage threshold; cleared after a successfully-entered normal operating mode or flash programming mode 0 no power-on reset bit symbol description value function
2004 mar 22 37 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.4 s ystem diagnosis register this register allows status information to be read back from the UJA1061. table 5 diag - system diagnosis register (address 00) bit description bit symbol description value function 15, 14 a1, a0 register address 00 read system diagnosis register (diag) 13 rrs read register select 1 12 ro read only 1 read system diagnosis register without writing to mode register 0 read system diagnosis register and write to mode register 11 gsd ground shift diagnosis 1 system gnd is worse than selected threshold 0 system gnd is better than selected threshold 10 to 7 canfd can failure diagnosis 1111 txdc is clamped dominant 1110 rxdc is clamped dominant 1101 rxdc is clamped recessive 1100 bus is clamped dominant (dual failure situation) 1011 bus is clamped recessive (dual failure situation) 1010 reserved 1001 canh is shorted to canl (failure case 7) 1000 canl is shorted to v cc (failure case 6a) 0111 canl is shorted to vbat (failure case 6) 0110 canh is shorted to gnd (failure case 5) 0101 canl is shorted to gnd (failure case 4) 0100 canh is shorted to v cc (failure case 3a) 0011 canh is shorted to vbat (failure case 3) 0010 canl wire is interrupted (failure case 2) 0001 canh wire is interrupted (failure case 1) 0000 no failure 6, 5 linfd lin failure diagnosis 11 txdl is clamped dominant 10 lin is shorted to gnd (dominant clamped) 01 lin is shorted to vbat (recessive clamped) 00 no failure 4 v3d v3 diagnosis 1 ok; after a detected short-circuit; the bit is set again with activating v3 via the v3c control bits 0 fail; v3 is disabled due to a short circuit situation 3 v2d v2 diagnosis 1 ok; note 1 0 fail; v2 is disabled due to a short-circuit situation 2 v1d v1 diagnosis 1 ok; v1 always above ram retention threshold since last read access 0 fail; v1 was below ram retention threshold since last read access; bit is set again with read access
2004 mar 22 38 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 note 1. v2d becomes cleared upon a short-circuit situation on v2 (overload) while v2 is active. in parallel, v2 becomes disabled in order to protect the system from high current consumption. v2 will be restarted setting v2d with the following events: a) by setting can mode b) during a high-to-low transition of the ctc bit (physical layer control register) activating the can-transmitter c) during a transition from off-line into on-line d) during a transition from off-line into selective sleep mode. 1, 0 canmd can mode diagnosis 11 can is within active mode 10 can is within on-line mode 01 can is within selective sleep mode 00 can is within off-line mode bit symbol description value function
2004 mar 22 39 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.5 i nterrupt enable register this register, which can be written to only in normal and standby modes, allows setting/enabling certain interrupt events for the UJA1061 table 6 ie - interrupt enable register (address 01) bit description bit symbol description value function 15, 14 a1, a0 register address 01 read interrupt enable register 13 rrs read register select 1 read the interrupt register (int) 0 read the interrupt enable feedback register (ief) 12 ro read only 1 read the register selected by rrs without writing to interrupt enable register 0 read the register selected by rrs and write to interrupt enable register 11 wtie watchdog time-out interrupt enable (1) 1 a watchdog over?ow during standby causes an interrupt instead of a reset event 0 no interrupt forced upon over?ow; a reset is forced instead 10 otie over-temperature interrupt enable 1 exceeding or dropping below the temperature warning limit causes an interrupt 0 no interrupt forced 9 gsie ground shift interrupt enable 1 exceeding or dropping below the gnd shift limit causes an interrupt 0 no interrupt forced 8 spifie spi clock count failure interrupt enable 1 wrong number of clk cycles (more than, or less than 16) forces an interrupt; within start-up and restart mode, a reset is performed instead of an interrupt 0 no interrupt forced; spi access is ignored if wrong number of cycles is applied (more than, or less than 16) 7 batfie bat failure interrupt enable 1 falling edge at sense forces an interrupt 0 no interrupt forced 6 v2v3fie v2/v3 failure interrupt enable (2) 1 detection of a short-circuit at v2 or v3 forces an interrupt 0 no interrupt forced 5 canfie can failure interrupt enable 1 any change of the can failure status forces an interrupt 0 no interrupt forced 4 linfie lin failure interrupt enable 1 any change of the lin failure status forces an interrupt 0 no interrupt forced 3 wie wake interrupt enable 1 a negative edge at wake generates an interrupt in normal, flash or standby mode 0 a negative edge at wake generates a reset in standby mode 2 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1
2004 mar 22 40 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 notes 1. this flag is cleared automatically upon each overflow event. it has to be set in software each time the interrupt behaviour is required (fail-safe behaviour). 2. if v2 or v3 is shut down due to a short-circuit, or activation of v2 or v3 fails due to a short-circuit, the interrupt is forced. v2 can be activated again by clearing ctc (can transmitter control), setting can mode or via a wake-up event on can. v3 can be activated setting bit v3c to a value other than 00. 1 canie can interrupt enable 1 can-bus event results in a wake-up interrupt 0 can-bus event results in a reset 0 linie lin interrupt enable 1 lin-bus event results in a wake-up interrupt 0 lin-bus event results in a reset bit symbol description value function
2004 mar 22 41 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.6 i nterrupt e nable f eedback register this register allows the current setting of the interrupt enable bits to be read back. table 7 ief - interrupt enable feedback register (address 01) bit description bit symbol description value function 15, 14 a1, a0 register address 01 read interrupt enable feedback register 13 rrs read register select 0 12 ro read only 1 read the interrupt enable feedback register without writing to interrupt enable register 0 read the interrupt enable feedback register and write to interrupt enable (previous content is re?ected during read) 11 wtie watchdog time-out interrupt enable 1 a watchdog over?ow during standby mode causes an interrupt instead of a reset 0 no interrupt forced 10 otie over-temperature interrupt enable 1 exceeding or dropping below the temperature warning limit causes an interrupt 0 no interrupt forced 9 gsie ground shift interrupt enable 1 exceeding or dropping below the gnd shift limit causes an interrupt 0 no interrupt forced 8 spifie spi clock count failure interrupt enable 1 wrong number of clk cycles (more than, or less than 16) forces an interrupt; within start-up and restart mode, a reset is performed instead of an interrupt 0 no interrupt forced, spi access simply ignored if wrong number of cycles is applied (more than, or less than 16) 7 batfie bat failure interrupt enable 1 falling edge at sense forces an interrupt 0 no interrupt forced 6 v2v3fie v2/v3 failure interrupt enable 1 detection of a short circuit at v2 or v3 forces an interrupt 0 no interrupt forced 5 canfie can failure interrupt enable 1 any change of the can failure status forces an interrupt 0 no interrupt forced 4 linfie lin failure interrupt enable 1 any change of the lin failure status forces an interrupt 0 no interrupt forced 3 wie wake-up interrupt enable 1 a negative edge at wake generates an interrupt in normal, flash or standby modes 0 a negative edge at wake generates a reset in standby mode 2 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 1 canie can interrupt enable 1 can-bus event results in a wake-up interrupt 0 can-bus event results in a reset 0 linie lin interrupt enable 1 lin-bus event results in a wake-up interrupt 0 lin-bus event results in a reset
2004 mar 22 42 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.7 i nterrupt register this register allows the cause of an interrupt event to be read. the register is cleared upon read access and upon any reset event. hardware makes sure that no interrupt event is lost in case there is a new interrupt forced while reading the register. the intn pin is forced high after reading the interrupt register for a defined period of time in order to make sure that there is always an edge event guaranteed at the intn pin. the interrupts can be classified into two classes: one in which the UJA1061 must react immediately due to timing-sensitive interrupts (spi clock can failure which needs an immediate resend of a new spi command, and bat failure which needs immediate saving of critical data into the non-volatile memory) one which does not need an immediate reaction (overtemp, ground shift, can and lin failures, v2 and v3 failures and the wake-ups via can, lin and wake. these interrupts will be signalled in normal mode and flash mode via the intn pin to the microcontroller once per watchdog period (maximum). table 8 int - interrupt register (address 01) bit description bit symbol description value function 15, 14 a1, a0 register address 01 read interrupt register (int) 13 rrs read register select 1 12 ro read only 1 read the interrupt register without writing to interrupt enable register 0 read the interrupt register and write to interrupt enable register 11 wti watchdog time-out interrupt 1 a watchdog over?ow has occurred during standby mode 0 no interrupt 10 oti over-temperature interrupt 1 the temperature warning limit has been exceeded or has dropped below 0 no interrupt 9 gsi ground shift interrupt 1 the gnd shift limit has been exceeded or has dropped below 0 no interrupt 8 spifi spi clock count failure interrupt 1 wrong number of clk cycles (more than, or less than 16) during spi access; within start-up and restart modes, a reset is performed instead of an interrupt 0 no interrupt; spi access is ignored if wrong number of cycles is applied (more than, or less than 16) 7 batfi bat failure interrupt 1 falling edge at sense forces an interrupt 0 no interrupt 6 v2v3fi v2/v3 failure interrupt 1 short-circuit detected at v2 or v3 (details within system status register 1) 0 no interrupt 5 canfi can failure interrupt 1 can failure status has changed 0 no interrupt 4 linfi lin failure interrupt 1 lin failure status has changed 0 no interrupt 3 wi wake-up interrupt 1 a negative edge at wake has been detected 0 no edge
2004 mar 22 43 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 2 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 1 cani can wake-up interrupt 1 there was a can-bus event resulting in a wake-up interrupt, if enabled 0 no wake-up via can 0 lini lin wake-up interrupt 1 there was a lin-bus event resulting in a wake-up interrupt, if enabled 0 no wake-up via lin bit symbol description value function
2004 mar 22 44 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.8 s ystem configuration register this register, only accessible in normal and standby modes, allows the UJA1061 behaviour to be configured. table 9 sc - system con?guration register (address 10) bit description note 1. for fail-safe reasons, this bit is set automatically when entering the reset state. bit symbol description value function 15, 14 a1, a0 register address 10 select system con?guration register 13 rrs read register select 1 read the general purpose feedback register (gpf0) 0 read the system con?guration feedback register (scf) 12 ro read only 1 read register selected by rrs without writing to system con?guration register 0 read register selected by rrs and write to system con?guration register 11 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 10 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 9 gsthc gnd shift threshold control 1 - 1.5 v; exceeding this level forces an interrupt 0 - 0.75 v; exceeding this level forces an interrupt 8 rlc reset length control 1 (1) 20 ms system reset is selected; default after power-up 0 1 ms system reset is selected 7, 6 v3c v3 control 11 cyclic mode 2; 350 m s on/32 ms period 10 cyclic mode 1; 350 m s on/16 ms period 01 continuously on 00 off; also reset to 00 in fail-safe mode, or after a negative edge has been detected at the external rstn pin, or a short-circuit situation is detected at v3 5 v1rthc v1 reset threshold control 1 the reduced v1 undervoltage threshold is selected 0 the normal v1 undervoltage threshold is selected 4 v1cmc v1 current monitor control 1 an increasing v1 current causes a reset event if the watchdog was disabled during standby mode 0 an increasing v1 current just activates the watchdog again during standby mode 3 wen wake enable 1 wake-up functionality at wake pin enabled 0 wake-up functionality at wake pin disabled 2 wsc wake sample control 1 wake mode cyclic sample 0 wake mode continuous sample 1 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 0 ic inh control 1 inh/limp home pin high 0 inh/limp home pin ?oating
2004 mar 22 45 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.9 s ystem c onfiguration f eedback register this register allows the settings within the configuration register to be read back. table 10 scf - system con?guration feedback register (address 10) bit description bit symbol description value function 15, 14 a1, a0 register address 10 read system con?guration feedback register (scf) 13 rrs read register select 0 12 ro read only 1 read the system con?guration feedback register without writing to the system con?guration register 0 read the system con?guration feedback register and write to the system con?guration register (previous content re?ected) 11 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 10 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 9 gsthc gnd shift threshold control 1 - 1.5 v; exceeding this level may force an interrupt 0 - 0.75 v; exceeding this level may force an interrupt 8 rlc reset length control 1 20 ms system reset is selected; default after power-up 0 1 ms system reset is selected 7, 6 v3c v3 control 11 cyclic mode 2; 350 m s on/32 ms period 10 cyclic mode 1; 350 m s on/16 ms period 01 continuously on 00 off 5 v1rthc v1 reset threshold control 1 the reduced v1 undervoltage threshold is selected 0 the normal v1 undervoltage threshold is selected 4 v1cmc v1 current monitor control 1 an increasing v1 current causes a reset event if the watchdog was disabled 0 an increasing v1 current just activates the watchdog again 3 wen wake enable 1 wake-up functionality at wake pin enabled 0 wake-up functionality at wake pin disabled 2 wsc wake sample control 1 wake mode cyclic sample 0 wake mode continuous sample 1 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 0 ic inh control 1 inh pin high 0 inh pin ?oating
2004 mar 22 46 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.10 p hysical l ayer c ontrol register this register has write access only in normal and standby modes; it allows the can and the lin physical layer to be configured. table 11 plc - physical layer control register (address 11) bit description bit symbol description value function 15, 14 a1, a0 register address 11 select physical layer control register 13 rrs read register select 1 read the general purpose feedback register 1 (gpf1) 0 read the physical layer control feedback register (plcf) 12 ro read only 1 read the register selected by rrs without writing to the physical layer control register 0 read the register selected by rrs and write to physical layer control register 11 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 10 cpnc can partial networking control 1 allows selective sleep state to be entered; cleared whenever the UJA1061 enters on-line or active mode 0 no selective sleep mode allowed (default) 9 cotc can off-line time control 1 256 ms time until can falls into off-line (400 ms after wake-up) 0 64 ms time until can falls into off-line (400 ms after wake-up) 8 ctc can transmitter control 1 (1) can transmitter is disabled; allows setting listen only behaviour; set also due to a detected short at v2 or a rxdc recessive or txdc dominant clamping failure 0 can transmitter is enabled 7 crc can receiver control 1 (2) txd signal is forwarded to rxd during can transmitter off 0 txd signal is not forwarded to rxd during can transmitter off 6 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 5 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 4 lsc lin slope control 1 up to 10 kbit/s 0 up to 20 kbit/s 3 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 2 l42c lin 42 v control 1 lin termination supplied out of bat42 0 lin termination is always related to bat14
2004 mar 22 47 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 notes 1. setting this bit actively under software control after a detected short-circuit on v2 restarts v2. 2. setting this bit allows a local self-test of the node without affecting the can bus wires. his bit should not be set during normal communication. 1 lwen lin wake-up enable 1 wake-up via the lin bus enabled 0 wake-up via the lin bus disabled 0 ltc lin transmitter control 1 lin transmitter is disabled; allows setting listen only behaviour 0 lin transmitter is enabled bit symbol description value function
2004 mar 22 48 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.11 p hysical layer control feedback register this register allows the can and the lin physical layer configuration to be read back. table 12 plcf - physical layer control feedback register (address 11) bit description bit symbol description value function 15, 14 a1, a0 register address 10 read the physical layer control feedback register (plcf) 13 rrs read register select 0 12 ro read only 1 read the physical layer control feedback register without writing to physical layer control register 0 read the physical layer control feedback register and write to physical layer control register (previous setting will be re?ected) 11 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 10 cpcn can partial networking control 1 allows selective sleep state to be entered; cleared whenever the UJA1061 enters on-line or active mode 0 no selective sleep mode allowed (default) 9 cotc can off-line time control 1 256 ms time until can falls into off-line (400 ms after wake-up) 0 64 ms time until can falls into off-line (400 ms after wake-up) 8 ctc can transmitter control 1 can transmitter is disabled; allows setting listen only behaviour; set also due to a detected short at v2 0 can transmitter is enabled 7 crc can receiver control 1 txd signal is forwarded to rxd during can transmitter off 0 txd signal is not forwarded to rxd during can transmitter off 6 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 5 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 4 lsc lin slope control 1 up to 10 kbit/s 0 up to 20 kbit/s 3 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 2 l42c lin 42 v control 1 lin termination supplied out of bat42 0 lin termination is always related to bat14
2004 mar 22 49 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 1 lwen lin wake-up enable 1 wake-up via the lin bus enabled 0 wake-up via the lin bus disabled 0 ltc lin transmitter control 1 lin transmitter is disabled; allows setting listen only behaviour 0 lin transmitter is enabled bit symbol description value function
2004 mar 22 50 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.12 s pecial m ode register this register is only accessible in start-up mode after the first battery connection (bat42) and allows special UJA1061 modes to be written only once. another write access is possible only by removing the power from pin bat42. table 13 spe - special mode register (address 01) bit description note 1. setting of isdm is possible only via writing to the special mode register and is possible only once after supplying the bat42 voltage to the UJA1061 for the first time. the access of the special mode register has to be executed before the watchdog is initialized, that is before the first writing to the mode register. resetting is possible at any time via the mode register. a set isdm flag disables all reset events caused by the UJA1061 during normal mode (with the exception of wrong mode register code resets), disables the interrupt time monitoring function during normal mode, and the watchdog initialization time, the reset monitoring and the transitions to fail safe with the exception of a v1-undervoltage longer than 256 ms. this bit is set automatically if pin test is forced to 7 v or higher during power-on of the UJA1061 (watchdog off test mode or device level test mode). watchdog trigger failures result only in the interrupt. bit symbol description value function 15, 14 a1, a0 register address 01 select special mode register 13 rrs read register select 0 read the interrupt enable feedback register (ief) 1 read the interrupt feedback register (int) 12 ro read only 1 read the register selected by rrs without writing to the special mode register 0 read the register selected by rrs and write to the special mode register 11 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 10 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 9 isdm initialize software development mode 1 no watchdog reset, no interrupt monitoring, no reset monitoring, no transitions to fail-safe mode, only during a v1 undervoltage longer than 256 ms; note 1 0 normal watchdog interrupt, reset monitoring and fail-safe behaviour 8 errem error-pin emulation mode 1 pin en re?ects the content of the canfd register: logic 1 if canfd = 0000 (no error) logic 0 if canfd is not 0000 (error) 0 pin en behaves as an enable pin (see section 6.5.2) 7 lhm limp home mode 1 ic-bit within system con?guration register is set entering fail-safe mode (limp home function) 0 ic-bit is cleared within system con?guration register when entering fail-safe mode (inh function) 6to0 - reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1
2004 mar 22 51 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.14.13 g eneral p urpose registers general purpose registers 0 and 1 have write access in start-up, restart mode and flash mode only to allow general bits to be written to the UJA1061. table 14 gp0 - general purpose register 0 (address 10) bit description note 1. during power-up, the bits of the general purpose register 0 (gp0) will be loaded with a device identification code consisting of the sbc type and sbc version. bit 11 of gp0 will reflect a logic 0 indicating the content of this register to be the device identification code after power-on of the sbc. once written to this register, bit 11 will be set to a permanent logic 1 indicating that the device code has been overwritten with application-specific information. bit 11 cannot be reset any more with software control. bit 11 will be cleared again with the next power-on condition at pin bat42 with reloading the device code into gp0. table 15 gp1 - general purpose register 1 (address 11) bit description 6.14.14 g eneral p urpose f eedback registers general purpose feedback registers 0 and 1 allow the general bits to be read from the UJA1061. bit symbol description value function 15, 14 a1, a0 register address 10 read the general purpose feedback register 0 (gpf0) 13 rrs read register select 1 read the general purpose feedback register 0 (gpf0) 0 read the system con?guration feedback register (scf) 12 ro read only 1 read the register selected by rrs without writing to the general purpose register 0 (gp0) 0 read the register selected by rrs and write to the general purpose register 0 (gp0) 11 to 0 gp0 general purpose bits 1 the relevant general purpose bit has been set; note 1 0 the relevant general purpose bit has been cleared; note 1 bit symbol description value function 15, 14 a1, a0 register address 11 select general purpose register 1 13 rrs read register select 1 read the general purpose feedback register 1 (gpf1) 0 read the physical layer control feedback register 1 (plcf) 12 ro read only 1 read the register selected by rrs without writing to the general purpose register 1 (gp1) 0 read the register selected by rrs and write to the general purpose register (gp1) 11 to 0 gp0 general purpose bits 1 the relevant general purpose bit has been set 0 the relevant general purpose bit has been cleared
2004 mar 22 52 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 table 16 gpf0 - general purpose feedback register 0 (address 10) bit description note 1. during power-up, the bits of the general purpose register 0 (gp0) will be loaded with a device identification code consisting of the sbc type and sbc version. bit 11 of gp0 will reflect a logic 0 indicating the content of this register to be the device identification code after power-on of the sbc. once written to this register, bit 11 will be set to a permanent logic 1 indicating that the device code has been overwritten with application-specific information. bit 11 cannot be reset any more with software control. bit 11 will be cleared again with the next power-on condition at pin bat42 with reloading the device code into gp0. table 17 gp1 - general purpose feedback register 1 (address 11) bit description bit symbol description value function 15, 14 a1, a0 register address 10 read general purpose feedback register 0 (gpf0) 13 rrs read register select 1 12 ro read only 1 read the general purpose feedback register 0 (gpf0) without writing to the physical layer control register or the general purpose register 0 0 read the general purpose feedback register 0 and write to the system con?guration register or the general purpose register 0 11 to 0 gp0 general purpose bits 1 the relevant general purpose bit has been set; note 1 0 the relevant general purpose bit has been cleared; note 1 bit symbol description value function 15, 14 a1, a0 register address 1 read general purpose feedback register 1 (gpf1) 13 rrs read register select 1 12 ro read only 1 read the general purpose feedback register 1 (gpf1) without writing to the physical layer control register or the general purpose register 1 0 read the general purpose feedback register 1 and write to the physical layer control register or the general purpose register 1 11 to 0 gp1 general purpose bits 1 the relevant general purpose bit has been set 0 the relevant general purpose bit has been cleared
2004 mar 22 53 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.15 register con?gurations at reset many register contents are unaffected by an external reset event (edge at pin rstn), for example, the can physical layer register will not reset the bus failure information. since an externally-forced reset event sets the UJA1061 into start-up, the same behaviour will occur as in start-up mode with the exception of the v3 configuration flag v3c and the inh control flags (ic1 and ic2) in the system configuration register. table 18 mode register: status at reset table 19 system status register: status at reset note 1. depends on history. symbol name power-on start-up/ external reset restart nwp nominal watchdog period 256 ms start-up 256 ms start-up 256 ms start-up om operating mode wait on init wait on init wait on init sdm software development mode 000 en enable 0 (en = low) 0 (en = low) 0 (en = low) cm can mode 0 (auto) 0 (auto) 0 (auto) symbol name power-on start-up/ external reset (1) restart (1) rss reset source status 0000 0001 or 0010 or 0011 or 0100 or 0111 or 1000 or 1001 or 1010 or 1011 or 1101 or 1110 or 1111 0000 or 0110 or 1100 or 1110 lws level wake status 0 no change no change ews edge wake status 0 no change no change tws temperature warning status 0 actual status actual status sdms software development mode status 0 no change no change ens enable status 0 (en = low) 0 (en = low) 0 (en = low) pwons power-on status 1 0 0
2004 mar 22 54 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 table 20 system diagnosis register: status at reset table 21 interrupt enable and interrupt enable feedback register: status at reset interrupt register: status at reset table 22 system con?guration and system con?guration feedback registers: status at reset symbol name power-on start-up/ external reset restart gsd ground shift diagnosis 0 (ok) actual status actual status canfd can failure diagnosis 0000 actual status actual status linfd lin failure diagnosis 00 actual status actual status v3d v3 diagnosis 1 (ok) actual status actual status v2d v2 diagnosis 1 (ok) actual status actual status v1d v1 diagnosis 1 (ok) actual status actual status canmd can mode diagnosis 00 (off-line) actual status actual status symbol name power-on start-up/ external reset restart all all ?ags 0 (interrupt disabled) no change no change symbol name power-on start-up/ external reset restart all all ?ags 0 (no interrupt) 0 (no interrupt) 0 (no interrupt) symbol name power-on start-up/ external reset restart gsthc gnd shift level threshold control 0( - 0.75 v) no change no change rlc reset length control 1 (long) no change 1 (long) v3c v3 control 00 (off) no change/00 (off) at external reset no change v1rtc v1 reset threshold control 0 (normal) no change 0 (normal) v1cmc v1 current monitor control 0 (no reset) no change no change wen wake enable 1 (enabled) no change no change wsc wake sample control 0 (control) no change no change ic inh control 0 (?oating) 0 (?oating) if external reset or at v1 undervoltage 0 (?oating)
2004 mar 22 55 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 table 23 physical layer control and physical layer control feedback registers: status at reset table 24 special mode register: status at reset table 25 general purpose and general purpose feedback register 0: status at reset table 26 general purpose and general purpose feedback register 1: status at reset symbol name power-on start-up/ external reset restart cpnc can partial networking control 0 (no control) no change no change cotc can off-line time control 1 no change no change ctc can transmitter control 0 (on) no change no change crc can receiver control 0 (rxdc represents can-bus signals) no change no change lsc lin slope control 0 (20 kbit/s) no change no change l42c lin 42 v control 0 (bat14) no change no change lwrc lin wake-up reset control 1 (enabled) no change no change ltc lin transmitter control 0 (transmitter on) no change no change symbol name power-on start-up/ external reset restart isdm initial software development mode 0 (no) 0 (no change) 0 (no change) errem error pin emulation mode 0 (no) no change no change lhm limp home mode 0 (no) 0 (no change) 0 (no change) symbol name power-on start-up/ external reset restart gp0 11 general purpose bit 11: 1 for sbc identity; 0 for general user purpose 011 gp0 10 to 7 general purpose bits 10 to 7 (version) 0011 (n1c) no change no change gp0 6 to 0 general purpose bits 6 to 0 (sbc type) 0000001 (UJA1061) no change no change symbol name power-on start-up/ external reset restart gp1 general purpose bits 0 no change no change
2004 mar 22 56 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.16 test modes 6.16.1 s oftware development mode the software development mode is intended to support software developers, writing and pre-testing the application software without working around the watchdog triggering and without unwanted jumps to fail-safe mode. this allows easy software development and debugging without forcing unintended reset events. instead of resets caused by watchdog overflows, window missing, interrupt time-out or exceeded start-up time an interrupt will be forced instead of a reset. once this mode is set, any watchdog trigger failure will not result in a reset, only in an interrupt, if enabled. nevertheless the reset source information and interrupt information continues to be provided to the software as if there was a real reset event. furthermore, the interrupt monitoring, forcing a low signal at pin rstn if not serving the interrupt in time, is disabled too. also the watchdog initialization time monitoring and reset monitoring have been disabled.thus the software can already trigger the watchdog as intended for the final software version and any watchdog interrupt gives an indication about pending watchdog trigger problems. once there are no further unwanted interrupts, the watchdog can be used as intended. in addition to the disabling of the watchdog activity, the interrupt monitoring and the reset monitoring, any transition to fail-safe mode is disabled; the UJA1061 then stays in the mode in which the problem occurred. transitions to restart mode are still possible, but not to fail-safe mode. a v1 undervoltage of more than 256 ms is the only exception that results in entering fail-safe mode and this is in order is to protect the UJA1061. the software development mode can be used also for testing and/or measuring many parameters/mode changes during the pretest and final test programs. for fail-safe reasons, the software development mode can be activated by setting the isdm bit via the special mode register. this mode can be set only once after a first battery connection before the watchdog is initialized, this means within the 256 ms start-up period and before the first spi write-access to any other register. a second possibility to enter this mode is a high level (7 to 8 v) at pin test before the battery is applied to bat42. leaving this development mode and entering the normal operating behaviour is executed after disabling the sdm bit at any time during a write-access to the mode register. it should be noted that the sdm bit has to confirm the software development mode with each mode register access, even if the test pin is pulled to a voltage higher than (7 to 8) v. entering the software development mode again is possible only by disconnection of the battery supply (bat42) thus forcing a new power-on period for the UJA1061. the watchdog behaviour within standby and sleep mode is not affected by the sdm bit. this allows the cyclic wake-up behaviour to be evaluated during the standby or sleep mode of the UJA1061.
2004 mar 22 57 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 6.16.2 f orced n ormal mode for system evaluation purposes the UJA1061 contains the forced normal mode. during this test the UJA1061 operates in normal mode with disabled watchdog. all the voltage regulators are switched on. the can-transceiver operates in active and automatic fault-tolerant mode. the lin-transceiver operates in active mode and this mode can be activated only with a stable high-level (12 v) at pin test during the first battery connection. leaving this mode and entering the normal operating mode will be executed after releasing the test pin (level at 0 v). entering the forced normal mode again is possible only by disconnection of the battery supply (bat42) thus forcing a new power-on period for the UJA1061. the behaviour of the UJA1061 in forced normal mode is as follows: spi access (writing and reading) is blocked watchdog is disabled interrupt monitoring is disabled reset monitoring is disabled UJA1061 is held in normal mode; any transition to fail-safe mode is disabled and the UJA1061 remains in the mode in which the problem occurred; the only exception that results in entry into fail-safe mode is a v1 undervoltage longer than 256 ms as self-protection of the sbc v1 is started with the defined reset (20 ms low-to-high) v2 is on; undervoltage protection is still active, which results in v2 switching off; v2 can only be switched on again by disconnecting the test and bat pins and then reconnecting first the test pin and later the bat42/14 pin can and lin are in active mode and cannot switch to an off-line mode v3 is on; undervoltage protection is still active, which results in v3 switching off; v3 can only be switched on again by disconnecting the test and bat pins and then reconnecting first the test pin and later the bat42/14 pin inh is on sysinh is on in the case of a v1 undervoltage, a reset will be performed until v1 is restored (normal behaviour); the UJA1061 stays in forced normal mode; in case of a continuous overload at v1 (> 256 ms) fail-safe mode will be entered; v1 can be switched on again only by disconnecting the test and bat pins and then reconnecting first the test pin and later the bat42/14 pin pulling pin rstn low externally will not result in leaving the forced normal mode, the UJA1061 will ignore external resets; this is because the flash programmer uses pin rstn for other purposes (i.e. the flash programmer uses the rstn line for serial communication entering/preparing the flash rom routines with special sequences) no reset lengthening directly after pin rstn is released, pin en will go high; a low value on pin rstn (but not an external low value) will result in a low value on the pin en; pin en stays active all the time during forced normal mode.
2004 mar 22 58 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 7 limiting values in accordance with the absolute maximum rating system (iec 60134); all voltages are referenced to gnd. notes 1. in accordance with iec 60747-1. an alternative definition of virtual junction temperature t vj is: t vj =t amb +p d r th(vj-amb) , where r th(vj-amb) is a fixed value to be used for the calculation of t vj . the rating for t vj limits the allowable combinations of power dissipation (p d ) and ambient temperature (t amb ). 2. human body model (hbm): c = 100 pf; r = 1.5 k w . 3. machine model (mm): c = 200 pf; l = 0.75 m h; r = 10 w . symbol parameter conditions min. max. unit v bat42 42 v supply voltage - 0.3 +60 v load dump; t 500 ms - +60 v v bat14 14 v supply voltage - 0.3 +33 v load dump; t 500 ms - +50 v v txdc , v rxdc , v txdl , v rxdl , v rstn , v intn , v sdo , v sdi , v sck , v scs , v en dc voltages on pins txdc, rxdc, txdl, rxdl, rstn, intn, sdo, sdi, sck, scs and en - 0.3 v v1 + 0.3 v v inh , v wake , v v3 , v sysinh dc voltage at pins inh, wake, v3 and sysinh - 0.3 v bat42 + 0.3 v v canl , v canh , v lin dc voltage at pins canl, canh and lin - 60 +60 v v trt transient voltage at pins canl, canh and lin (iso6737) tested with a special application - 150 +100 v v rth , v rtl , v rtlin dc voltage at pins rth, rtl and rtlin - 60 v bat42 + 1.2 v v v1 , v v2 dc voltage at pins v1 and v2 - 0.3 +5.5 v v sense dc voltage at pin sense - 0.3 v bat42 + 1.2 v v test dc voltage at pin test - 0.3 12 v t stg storage temperature - 55 +150 c t amb ambient temperature - 40 +125 c t vj virtual junction temperature note 1 - 40 +150 c v esd electrostatic discharge voltage hbm; note 2 at pins canh, canl, rth, rtl, lin, rtlin, wake, bat14, bat42, v3, sense - 8.0 +8.0 kv at any other pin - 2.0 +2.0 kv mm; note 3; at any pin - 200 +200 v
2004 mar 22 59 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 001aaa345 17 k/w v1 power 43 k/w 4 k/w v2 power 29 k/w v3 power 1 k/w remainder t vj t case (heatsink) t amb r th(c-a) fig.14 thermal model of httsop32 package. the value r th(c-a) depends on the pcb used. without any pcb, r th(c-a) = 113 k/w. with a 4-layer jedec pcb with an effective area of 50 x 50 mm, rth(c-a) = 32.5 k/w.
2004 mar 22 60 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 8 dc characteristics t vj = - 40 to +150 c, v bat42 = 5.5 to 52 v, v bat14 = 5.5 to 27 v; unless otherwise speci?ed. all voltages are de?ned with respect to ground. positive currents ?ow into the ic. all parameters are guaranteed over the virtual junction temperature range by design. products are 100% tested at 125 c ambient temperature on wafer level (pre-testing). cased products are 100% tested at 25 c ambient temperature (?nal testing). both pre-testing and ?nal testing use correlated test conditions to cover the speci?ed temperature and power supply voltage range. symbol parameter conditions min. typ. max. unit supply (pin bat42) i bat42 supply current bat42 sleep mode; v3 off or in cyclic mode; can and lin in off-line; i inh = i sysinh = i rth = i rtl = i rtlin = 0; v wake =v bat42 - 50 100 m a sleep mode; v3 continuously on; can and lin in off-line; i inh = i sysinh = i rth = i rtl = i rtlin =0; v wake =v bat42 - 60 120 m a sleep mode; v2 on; v3 continuously on; can in selective sleep mode or on-line; lin in off-line; i inh =i sysinh =i rth =i rtl = i rtlin = 0; v wake = v bat14 = v bat42 - 70 140 ma standby mode; v1, v2 on; v3 continuously on; can in selective sleep mode or on-line; lin in off-line; i inh =i sysinh =i rth = i rtl = i rtlin = 0; v wake =v bat42 - 70 140 m a normal mode; v1, v2, v3 on; can and lin in active mode; watchdog on; l42c = logic 0; i v3 =i inh =i sysinh =0; v wake =v bat42 ; v bat14 3 v bat42 - 70 140 m a normal mode; v1, v2, v3 on; can and lin in active mode; watchdog on; l42c = logic 0; i v3 =i inh =i sysinh =0; v wake =v bat42 ; v bat14 v bat42 - 500 1000 m a normal mode; v1, v2, v3 on; can and lin in active mode; watchdog on; l42c = logic 1; i v3 =i inh =i sysinh =0; v wake =v bat42 ; v bat14 2004 mar 22 61 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 supply (pin bat14) i bat14 supply current bat14 normal mode; v1, v2, v3 on; can and lin in active mode; can in single-wire mode; watchdog on; v txdc = 0 v (dominant), v txdl =0v (dominant); i v1 =i rth = i rtl = i rtlin = 0; no load on canh, canl and lin - 19 28 ma normal mode; v1, v2, v3 on; can and lin in active mode; can in differential mode; watchdog on; v txdc = 0 v (dominant); v txdl =0v (dominant); i v1 =i rth = i rtl = i rtlin = 0; no load on canh, canl and lin - 13 21 ma normal mode; v1, v2 and v3 on; can and lin in active mode; can in single-wire mode; watchdog on; v txdc =v v1 (recessive); v txdl = 0 v or v v1 (dominant or recessive); i v1 =i rth = i rtl = i rtlin = 0; no bus failure; no load on canh, canl and lin - 10 19 ma normal mode; v1, v2 and v3 on; can and lin in active mode; can in differential mode; watchdog on; v txdc =v v1 (recessive), v txdl = 0 v or v v1 (dominant or recessive); i v1 = i rth = i rtl = i rtlin = 0; no load on canh, canl and lin - 6.5 12 ma standby mode; v1, v2, v3 on; can in selective sleep mode or on-line; lin in off-line; can in single-wire mode; watchdog on; v txdc = v txdl =v v1 ; i v1 =i rth = i rtl = i rtlin =0 - 917 ma standby mode; v1, v2, v3 on; can in selective sleep mode or on-line; lin in off-line; can in differential mode; watchdog on; v txdc = v txdl =v v1 ; i v1 =i rth = i rtl = i rtlin =0 - 611 ma standby mode; v1 on; v2, v3 off; can and lin in off-line; i v1 =i rth = i rtl = i rtlin =0 - 250 450 m a symbol parameter conditions min. typ. max. unit
2004 mar 22 62 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 i bat14 (cont.) supply current bat14 (cont.) sleep mode; v1, v2 off; v3 on; can in selective sleep mode or on-line; lin in off-line; i rth =i rtl = i rtlin =0 - 611 ma sleep mode; v1, v2 off; v3 on; can and lin in off-line; i rth = i rtl = i rtlin = 0; v bat14 >v bat42 - 15 30 m a sleep mode; v1, v2 off; v3 on; can and lin in off-line; i rth = i rtl = i rtlin = 0; v bat14 2004 mar 22 63 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 v det(uv)(v1) undervoltage detection and activation levels of reset v bat14 = 14 v; v1rthc = logic 0 0.88 v v1(nom) 0.90 v v1(nom) 0.92 v v1(nom) v v bat14 = 14 v; v1rthc = logic 1 0.68 v v1(nom) 0.70 v v1(nom) 0.72 v v1(nom) v v hys(reset) hysteresis of reset level v bat14 = 14 v; v1rthc = logic 0 0.01 v v1(nom) 0.02 v v1(nom) 0.04 v v1(nom) v v ram(v1) ram content lost monitor level v bat14 = 14 v 0.40 v v1(nom) 0.45 v v1(nom) 0.50 v v1(nom) v i thh(v1) undercurrent threshold for watchdog enable - 2 - 4 - 6ma i thl(v1) undercurrent threshold for watchdog disable - 1.5 - 3 - 5ma i hys(th)(v1) undercurrent threshold hysteresis 0.5 1 1.5 ma i v1 output current capability v bat14 =7v - 300 tbf ma v bat14 = 8 to 27 v - 100 - 200 ma voltage source (pin v2) v v2 supply voltage v bat14 = 9 to 16 v; i v2 = - 100 to - 10 ma 4.8 5.0 5.2 v v bat14 = 14 v; t j =25 c, i v2 = - 10 ma 4.95 5.0 5.05 v d v v2 supply voltage regulation load regulation v bat14 = 9 to 16 v; i v2 = - 10 ma; t j =25 c - tbf 25 mv v bat14 =14v; i v2 = - 100 to - 10 ma; t j =25 c - tbf 50 mv d v2(t) voltage drift with temperature v bat14 =14v; - 40 c 2004 mar 22 64 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 42 v inhibit output (pin sysinh) v bat42-sysinh v bat42 to v sysinh voltage drop i sysinh = - 0.2 ma -- 1.0 v ? i l ? leakage current v sysinh =0v -- 5 m a inhibit output (pin inh) v bat14-inh v bat14 to v inh voltage drop i inh = - 10 m a - 0.7 1.0 v i inh = - 200 m a - 1.2 2.0 v ? i l ? leakage current v inh =0v -- 5 m a wake input (pin wake) v det(wake) wake detection threshold detection level 2.0 3.3 4.5 v release level 2.0 3.5 4.5 v v hys(det)wake detection threshold hysteresis 100 200 500 mv i wake pull-up input current v wake =0v - 10 -- 4 m a serial peripheral interface inputs (pins sdi, sck, scs) v th(il) low-level input threshold voltage - 0.3 - 0.3 v v1 v v th(ih) high-level input threshold voltage 0.7 v v1 - v v1 + 0.3 v d v hys(th) hysteresis of input threshold voltage 200 - 400 mv r pd(sck) pull-down resistor at pin sck v sck =2v; v v1 3 2 v 50 130 400 k w r pd(scs) pull-down resistor at pin scs v scs =1v; v v1 3 2 v 50 130 400 k w i sdi input leakage current at pin sdi v sdi =0tov v1 - 5 - +5 m a serial peripheral interface data output (pin sdo) i ol low-level output current v o = 0.4 v 1.6 - tbf ma i oh high-level output current v o =v v1 - 0.4 v tbf -- 1.6 ma i loz off-state output leakage current v o =0tov v1 - 5 - +5 m a reset push-pull input/output (pin rstn) v th(il) low-level input threshold voltage - 0.3 - +0.3 v v1 v v th(ih) high-level input threshold voltage 0.7 v v1 - v v1 + 0.3 v d v hys(th) hysteresis of input threshold voltage 200 - 400 mv i ol low-level output current v o = 0.4 v 50 - 1000 m a symbol parameter conditions min. typ. max. unit
2004 mar 22 65 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 i oh high-level output current v o =v v1 - 0.4 v; v1 = on - 1.6 -- 0.5 ma v ol low-level output voltage with v1 low i ol =20 m a; v v1 = 1.2 v 0 - 0.4 v enable output (pin en) i ol low-level output current v o = 0.4 v tbf - tbf ma i oh high-level output current v o =v v1 - 0.4 v tbf -- 1.6 ma v ol low-level output voltage i ol =20 m a; v v1 = 1.2 v 0 - 0.4 v interrupt open-drain output (pin intn) i ol low-level output current v o = 0.4 v 1.6 - tbf ma can-bus transmit data input (pin txdc) v il low-level input voltage - 0.3 - +0.3 v v1 v v ih high-level input voltage 0.7 v v1 - v v1 + 0.3 v r pu txdc pull-up resistor v txdc =0v 5 12 25 k w can-bus receive data output (pin rxdc) i ol low-level output current v rxdc = 0.4 v 1.6 - tbf ma i oh high-level output current v rxdc =v v1 - 0.4 v tbf -- 1.6 ma can-bus lines (pins canh and canl) v dif(canh-canl) differential receiver threshold voltage active mode, on-line or selective sleep mode; v v2 = 5 v; no failures and bus failures h//, l//, hxgnd and lxvcc - 3.5 - 3.15 - 2.8 v v se(canh) pin canh single ended receiver threshold voltage active mode, on-line or selective sleep mode; v v2 = 5 v; bus failures lxgnd, lxbat and hxl 1.45 1.7 1.95 v v se(canl) pin canl single ended receiver threshold voltage active mode, on-line or selective sleep mode; v v2 = 5 v; bus failures hxbat and hxvcc 3.05 3.3 3.55 v v det(hxbat) , v det(lxbat) detection threshold voltage for bus failures hxbat and lxbat active mode, on-line or selective sleep mode; v v2 =5v 6.5 7.3 8.0 v v det(gsd)(canh) pin canh ground shift detection threshold voltage active mode; v v2 =5v v spi bit gsdth = logic 0 - 1.25 - 0.75 - 0.25 v spi bit gsdth = logic 1 - 2.0 - 1.5 - 1.0 v symbol parameter conditions min. typ. max. unit
2004 mar 22 66 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 v wu(canh) pin canh wake-up threshold voltage off-line 2.5 3.2 3.9 v v wu(canl) pin canl wake-up threshold voltage off-line 1.1 1.8 2.5 v d v wu(canh-canl) wake-up threshold difference voltage canh to canl; off-line 0.8 1.4 - v v o(reces) canh recessive output voltage active mode, on-line or selective sleep mode; v v2 = 4.75 to 5.25 v; v txdc =v v2 -- 0.2 v canl recessive output voltage active mode, on-line or selective sleep mode; v v2 = 4.75 to 5.25 v; v txdc =v v2 v v2 - 0.2 -- v v o(dom) canh dominant output voltage active mode, on-line or selective sleep mode; v txdc =0v;v v2 =5v; i canh = - 40 ma v v2 - 1.4 -- v canl dominant output voltage active mode, on-line or selective sleep mode; v txdc =0v;v v2 =5v; i canl = - 40 ma -- 1.4 v i o(canh) pin canh output current active mode; v canh =0v; v txdc =0v; v v2 =5v - 100 - 75 - 45 ma auto mode; v canh =0v; v bat14 =14v -- 0.25 -m a i o(canl) pin canl output current active mode; v canl =5v; v txdc =0v; v v2 =5v 45 75 100 ma auto mode; v canl =14v; v bat14 =14v - 0 -m a can termination resistor (pin rth) r sw(rth) switch-on resistance measured between rth and gnd; active mode, on-line or selective sleep; ? i o ? = 10 ma; v txdc =5v - 50 100 w v o(rth) output voltage off-line; i o = 100 m a - 0.7 1.0 v i o(rth) pin canh output current during bus failure active mode; v rth =v canh =v v2 =5v - 75 -m a can termination resistor (pin rtl) r sw(rtl) switch-on resistance active mode, on-line or selective sleep; ? i o ? = 10 ma; v txdc =5v; v v2 =5v - 50 100 w i o(rtl) output current off-line; v rtl =0v - 1.0 - 0.3 - 0.1 ma v o(rtl) output voltage off-line; r rtl =10m w 6 8 11 v off-line; i rtl = - 100 m a 4.5 7 11 v i o(rtl) output current during bus failure at canl active mode; v rtl =v canl =0v; v v2 =5v -- 75 -m a symbol parameter conditions min. typ. max. unit
2004 mar 22 67 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 transmit data input (pin txdl) v il low level input voltage - 0.3 - 0.3 v v1 v v ih high-level input voltage 0.7 v v1 - v v1 + 0.3 v r pu txdl pull-up resistor v txdl = 0 v 5 12 25 k w receive data output (pin rxdl) i oh high-level output current v rxdl =v v1 - 0.4 v tbf -- 0.4 ma i ol low-level output current v rxdl = 0.4 v 0.4 - tbf ma temperature detection t j(warning) high junction temperature warning level 160 175 190 c lin-bus line (pin lin) v o(dom) lin dominant output voltage normal mode; v txdl =0v l42c = logic 0; v bat14 = 7.0 to 27 v; r bat14-lin = 500 w 0 - 0.20 v bat14 v l42c = logic 1; v bat42 3 18 v; i lin = - 20 ma 0 - 1.4 v i lih high-level input leakage current v lin =v bat42 ; v txdl =v v1 - 10 0 +10 m a i o(sc) short-circuit output current normal mode; v txdl =0v; t 2004 mar 22 68 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 note 1. not tested during production. lin-bus termination resistor connection (pin rtlin) v o output voltage i rtlin = - 10 m a; l42c = logic 1; v bat42 3 18 v v normal mode; v lin = 12 v (rec) 10.8 11.4 12.0 v normal mode; v lin =0v; t>t lin(dom) 91215v off-line mode; v lin = 12 v (rec) 9 12 15 v d v rtlin rtlin load regulation normal mode; i rtlin = - 10 m a to - 10 ma; l42c = logic 0 (v lin =v bat14(rec) ) or l42c = logic 1 (v lin(rec) =12v; v bat42 3 18 v) - 250 500 mv i o(pu) rtlin pull-up current normal mode; v rtlin =0v; v lin = 0 v (t > t lin(dom) ) - 150 - 75 - 35 m a off-line mode; v rtlin =0v; l42c = logic 0 (v lin =v bat14(rec) ) or l42c = logic 1 (v lin(rec) =12v; v bat42 3 18 v) - 150 - 75 - 35 m a i o(rtlin) low-level leakage current off-line mode; v rtlin =0v; v lin = 0 v (t > t lin;dom ) - 10 0 +10 m a test input (pin test) v th(test) threshold voltage for entering watchdog-off mode 3 5 7 v threshold voltage for entering forced normal mode 8 10 12 v r (pd)test pull-down resistor between pin test and gnd 2 4 8 k w symbol parameter conditions min. typ. max. unit
2004 mar 22 69 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 9 ac characteristics t vj = - 40 to + 150 c; v bat42 = 5.5 to 52 v; v bat14 = 5.5 to 27 v; unless otherwise speci?ed. all voltages are de?ned with respect to ground. positive currents ?ow into the ic. all parameters are guaranteed over the virtual junction temperature range by design. products are 100% tested at 125 c ambient temperature on wafer level (pre-testing). cased products are 100% tested at 25 c ambient temperature (?nal testing). both pre-testing and ?nal testing use correlated test conditions to cover the speci?ed temperature and power supply voltage range. symbol parameter conditions min. typ. max. unit serial peripheral interface (spi) timing (pins scs, sck, sdi, sdo) (see fig.19) t cyc clock cycle time 480 -- ns t lead enable lead time clock is low when spi select falls 240 -- ns t lag enable lag time clock is low when spi select rises 240 -- ns t sckh clock high time 190 -- ns t sckl clock low time 190 -- ns t su input data set-up time 100 -- ns t h input data hold time 100 -- ns t dov output data valid time pin sdo, c l =10pf -- 100 ns t ssh spi select high time 200 -- ns t ssl spi select low time 100 -- ns can transceiver (pins canl, canh, txdc and rxdc) t t(rec-dom) output transition time recessive to dominant 10 to 90 %; c1 = 10 nf; c2 = 0 nf; r1 = 100 w ; see figs 15 and 16 0.6 1.2 -m s t t(dom-rec) output transition time dominant to recessive 90 to 10 %; c1 = 1 nf; c 2=0nf; r1 = 100 w ; see figs 15 and 16 0.3 0.7 -m s t phl propagation delay txdc to rxdc (high to low transition) 50 % v txdc to 50 % v rxdc ; c1 = 10 nf; c 2 = 0 nf; r1 = 100 w ; see figs 15 and 16 - 1.0 1.8 m s t plh propagation delay txdc to rxdc (low to high transition) 50 % v txdc to 50 % v rxdc ; c1 = 1 nf; c 2 = 0 nf; r1 = 100 w ; see figs 15 and 16 - 1.2 1.9 m s t bus(fail)(det) bus failure detection time bus failure hxbat; active mode, on-line and selective sleep mode; v v2 =5v 7 - 38 m s bus failure hxvcc 1.6 - 8.0 ms bus failures lxgnd and hxl 0.9 - 1.6 ms bus failure lxbat; active mode, on-line and selective sleep mode; v v2 =5v 0.3 - 1.6 ms continuously dominant clamped can-bus detection time (start after detecting hxvcc); active mode, on-line and selective sleep mode; v v2 =5v 0.3 - 1.6 ms
2004 mar 22 70 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 t bus(fail)(recover) bus failure recovery time bus failure hxbat 125 - 750 m s bus failure hxvcc 0.3 - 1.6 ms bus failures lxgnd and hxl; active mode, on-line and selective sleep mode; v v2 =5v 7 - 38 m s bus failures lxgnd and hxl 0.9 - 1.6 ms bus failure lxbat; active mode, on-line and selective sleep mode; v v2 =5v 125 - 750 m s continuously dominant clamped can-bus active mode, on-line and selective sleep mode; v v2 =5v 1 - 5 m s t txdc(dom) txdc permanent dominant disable time active mode, on-line and selective sleep mode; v v2 =5v; txdc = logic 0 v 1.5 - 6ms t canh(d1) , t canl(d1) minimum dominant time ?rst pulse for wake-up on pins canh, canl off-line 7 - 38 m s t canh(rec) , t canl(rec) minimum recessive time pulse (after ?rst dominant) for wake-up on pins canh, canl off-line 3 - 10 m s t canh(d2) , t canl(d2) minimum dominant time second pulse for wake-up on pins canh, canl off-line 0 - 3 m s t canl(dom) canl dominant time entering normal mode and txdc goes dominant v canl > 8 v, ?rst dominant bit after entering active mode 3 - 10 m s t of?ine required recessive or dominant time for entering off-line on-line or selective sleep mode; cotc = logic 0; cm = logic 0 50 - 66 ms on-line or selective sleep mode; cotc = logic 1; cm = logic 0 200 - 265 ms on-line; cm = logic 0; coming out of off-line 400 - 530 ms t canh, t canl ground shift sampling time required for canh, canl voltage level active mode, on-line and selective sleep mode; v v2 = 5 v; txdc recessive 20 - 80 m s d t pc pulse count difference between canh and canl for failure detection bus failures h//, l//, hxgnd and lxvcc; active mode, on-line and selective sleep mode; v v2 =5v - 4 - pulses dominant pulse count on canh and canl for failure recovery bus failures h//, l//, hxgnd and lxvcc; active mode, on-line and selective sleep mode; v v2 =5v - 4 - pulses symbol parameter conditions min. typ. max. unit
2004 mar 22 71 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 lin-transceiver (pins lin, txdl and rxdl) ; note 1 d 1 duty factor 1 (2) v th(rec)(max) = 0.744 v sup ; v th(dom)(max) = 0.581 v sup ; lsc = logic 0; t bit =50 m s; l42c = logic 0 with v sup =v bat14 = 7 to 18 v or l42c = logic 1 with v bat42 3 18 v; v sup = internal 12 v 0.396 -- d 2 duty factor 2 (3) v th(rec)(min) = 0.284 v sup ; v th(dom)(min) = 0.422 v sup ; lsc = logic 0; t bit =50 m s; l42c = logic 0 with v sup =v bat14 = 7.6 to 18 v or l42c = logic 1 with v bat42 3 18 v; v sup = internal 12 v -- 0.581 d 3 duty factor 3 (2) v th(rec)(max) = 0.778 v sup ; v th(dom)(max) = 0.616 v sup ; lsc = logic 1; t bit =96 m s; l42c = logic 0 with v sup =v bat14 = 7 to 18 v or l42c = logic 1 with v bat42 3 18 v; v sup = internal 12 v 0.417 -- d 4 duty factor 4 (3) v th(rec)(min) = 0.251 v sup ; v th(dom)(min) = 0.389 v sup ; lsc = logic 1; t bit =96 m s; l42c = logic 0 with v sup =v bat14 = 7.6 to 18 v or l42c = logic 1 with v bat42 3 18 v; v sup = internal 12 v -- 0.590 t p(rx1)r , t p(rx1)f , t p(rx2)r , t p(rx2)f propagation delay of receiving nodes 1 and 2 c rxd =20pf -- 6 m s t p(rx1)(sym) symmetry of propagation delay of receiver rising edge with respect to falling edge; c rxd =20pf - 2 - +2 m s t bus(lin) dominant time for wake-up the lin-transceiver off-line 30 - 150 m s t lin(dom)(det) continuously dominant clamped lin-bus detection time active mode; lin = logic 0 v 40 - 160 ms t lin(dom)(rec) continuously dominant clamped lin-bus recovery time active mode tbf 1 tbf ms t txdl(dom)(dis) txdl permanent dominant disable time active mode; txdl = 0 v 20 - 80 ms t timeout time-out period between wake-up message and con?rm message selective sleep mode 115 - 285 ms symbol parameter conditions min. typ. max. unit
2004 mar 22 72 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 battery monitoring t bat42(l) bat42 low time for setting power-on reset ?ag 5 - 20 m s t sense(l) bat42 low time for setting bat fail ?ag 5 - 20 m s power supply v1 (pin v1) t v1(clt) v1 clamped low time during ramp-up of v1 start-up mode; v1 active 229 - 283 ms t v1mode low or high time to change from v1 = 3 v to v1 = 5 v and back v1 active 5 - 20 m s power supply v2 (pin v2) t 2(clt) v2 clamped low time during ramp-up v2 v2 active 28 - 36 ms power supply v3 (pin v3) t w(cs) cyclic sense period v3c = 10; see fig.12 180 - 220 m s v3c = 11; see fig.12 360 - 440 m s t on(cs) cyclic sense on-time v3c = 10; see fig.12 14 - 18 ms v3c = 11; see fig.12 28 - 36 ms wake-up input (pin wake) t wu input port ?lter time v bat42 =5to27v 10 - 120 m s v bat42 =27to52v 50 - 250 m s t su(cs) cyclic sense sample set-up time v3c = 11 or 10; see fig.12 310 - 390 m s watchdog t wd(etp) earliest trigger point programmed nominal watchdog period (nwp); normal mode 0.45 nwp - 0.55 nwp t wd(ltp) latest trigger point programmed nominal watchdog period (nwp); normal mode, standby and sleep mode 0.9 nwp - 1.1 nwp t wd(init) watchdog init period watchdog time-out in start-up mode 229 - 283 ms reset output (pin rstn) t rstn(ext) external reset monitoring time 229 - 283 ms t rstn(cht) clamped high time, pin rstn rstn driven low internally but rstn pin remains high 115 - 141 ms t rstn(int) interrupt monitoring time intn = logic 0 229 - 283 ms t rstnl reset lengthening time after internal or external reset has been released; rst = logic 0 0.9 - 1.1 ms after internal or external reset has been released; rst = logic 1 18 - 22 ms symbol parameter conditions min. typ. max. unit
2004 mar 22 73 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 notes 1. t bit = selected bit time, depends on lsc bits 50 or 96 m s (20 or 10.4 kbit/s respectively); bus load conditions (c bus /r bus ): 1 nf/1 k w ; 6.8 nf/660 w ; 10 nf/500 w ; see fig.18. 2. 3. interrupt output (pin intn) t intnh interrupt release after spi has read out the interrupt register 2 - 5 m s oscillator f osc oscillator frequency 460.8 512 563.2 khz symbol parameter conditions min. typ. max. unit d 1, d 3 t bus(rec)(min) 2t bit ------------------------------ = d 2, d 4 t bus(rec)(max) 2t bit ------------------------------- = mce635 r1 v2 + 5 v c1 20 canl 22 canh rxdc gnd bat42 bat14 20 pf 21 23 UJA1061 32 27 14 txdc 13 c2 r1 c1 c fig.15 timing test circuit for can-transceiver.
2004 mar 22 74 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 v rxdc v dif(canh-canl) v canh v canl v txdc mce636 t t(rec-dom) t t(dom-rec) t phl t plh 50 % 50 % 90 % 10 % 90 % 10 % 90 % 10 % 90 % 10 % 50 % 50 % 5 v 3.6 v 1.4 v 0 v 2.2 v - 3.2 v - 5 v fig.16 timing diagram can-transceiver. mce637 r1 c1 lin 25 rxdl gnd bat42 bat14 20 pf 12 v 23 UJA1061 32 27 5 txdl 3 fig.17 timing test circuit for lin-transceiver.
2004 mar 22 75 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 001aaa346 v txdl lin bus signal receiving node 1 receiving node 2 v sup (1) v rxdl1 v rxdl2 t bit t bus(dom)(max) t bus(rec)(min) v th(rec)(max) thresholds of receiving node 1 v th(dom)(max) v th(rec)(min) v th(dom)(min) t bus(dom)(min) t p(rx1)r t p(rx1)f t p(rx2)r t p(rx2)f t bus(rec)(max) t bit t bit thresholds of receiving node 2 fig.18 timing diagram lin-transceiver. (1) transceiver supply of transmitting node.
2004 mar 22 76 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 001aaa405 scs sck sdi sdo x x x msb lsb msb lsb t dov floating floating t h t su t sckl t sckh t lead t sck t lag t ssh fig.19 spi timing.
2004 mar 22 77 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 10 package outline unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot549-1 99-03-04 03-04-07 w m q a a 1 a 2 e h d h d l p detail x e z exposed die pad side e c l x (a 3 ) 0.25 1 16 32 17 y b h e 0.95 0.85 0.30 0.19 d h 5.1 4.9 e h 3.6 3.4 0.20 0.09 11.1 10.9 6.2 6.0 8.3 7.9 0.65 1 0.2 0.78 0.48 0.1 0.75 0.50 p v m a a htssop32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad sot549-1 a max. 1.1 0 2.5 5 mm scale pin 1 index
2004 mar 22 78 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 11 soldering 11.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 11.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson-t and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 11.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 11.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2004 mar 22 79 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 11.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2004 mar 22 80 philips semiconductors objective speci?cation low speed can/lin system basis chip UJA1061 12 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 13 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 14 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r16/01/pp 81 date of release: 2004 mar 22 document order number: 9397 750 11708

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